F29H859TU-Q1: ADC sample time

Hello Jenny,

Sample-and-hold time is really dependent on the external impedance seen by the ADC channel.  The input model of the F29x ADC (snippet from the datasheet below)

presents considerable impedance that is impacted by the external components as these would form multiple RC networks.  Calculating SH requires a few steps due to the complex RC network being formed with the external components.  This is outlined in the below section of the TRM:

The simplest way is just to use the SOC S/H calculator in SysConfig.  The calculator takes into account the pin capacitance, source RC components and calculates the sample and hold time given an LSB settling value (up to .25 LSB or 0.5 LSB) using charge-sharing principle.

For a well-matched input source, the smallest sample and hold time that the ADC allows is 75ns.  In terms of ACQPS, this is 75ns/(1/SYSCLK) - 1 or ACQPS value of 14 for device SYSCLK operation of 200MHz.  ACQPS is a 9-bit register that holds a minimum value of 0 and a maximum value of 511.  The largest sample and hold time is limited by ACQPS register so this will be (511 + 1)*(1/SYSCLK) or 2.56us.  Valid sample and hold time range of F29x device is from 75ns to 2.56us.  Reiterating again that sample and hold time is a function of the external source impedances and not just some random value set for ACQPS.

Regards,

Joseph