F29H859TU-Q1: pwm control in multicore application

Jenney Ni

Hi all,

Can a software-triggered Trip Zone (TZ) be controlled across multiple cores on the F29? For example, if ePWM1 is configured and running on CPU2, can code executing on CPU1 force a software TZ trip to shut down ePWM1?

Regards,

Jenney

28 days ago

0 Jenney Ni 27 days ago

TI__Intellectual 2310 points

Do we have any progress？

+1 Prarthan Bhatt 27 days ago in reply to Jenney Ni

TI__Mastermind 20486 points

Hi,

Yes Any CPU can read or write any peripheral register on F29x.

Thanks

0 Jenney Ni 27 days ago in reply to Prarthan Bhatt

TI__Intellectual 2310 points

Hi Prarthan，

Regarding the cross-core register access on F29, how are race conditions handled in the following scenarios?

If both CPUs attempt to set the software TZ at the same time, which one will take effect first?
If CPU1 is trying to trigger the fault (writing 1 to TZFRC), while CPU2 is simultaneously trying to clear the fault (writing 1 to TZCLR), will this cause a system crash or bus error? How does the hardware resolve this conflict?

Regards,

Jenney

+1 Prarthan Bhatt 26 days ago in reply to Jenney Ni

TI__Mastermind 20486 points

Jenney Ni said:
If both CPUs attempt to set the software TZ at the same time, which one will take effect first?

This will be handled by round robin arbitration on the peripheral bus.

Jenney Ni said:
If CPU1 is trying to trigger the fault (writing 1 to TZFRC), while CPU2 is simultaneously trying to clear the fault (writing 1 to TZCLR), will this cause a system crash or bus error? How does the hardware resolve this conflict?

No it will be handled by arbitration. User should handle this by communication through IPC or any other means between CPU's for right sequence as intended.

Thanks

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F29H859TU-Q1: pwm control in multicore application