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TMS320F28065: TMS320F28065: Should AdcOffsetSelfCal() use the same ACQPS and overlap mode as the application?

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Prodigy 10 points

Part Number: TMS320F28065

Hello, 

I have a question about the AdcOffsetSelfCal() function included in the Example_2806xAdcSoc example project for the TMS320F28065.
I sampled VREFLO using AdcOffsetSelfCal() and plotted the ADC conversion results under the following conditions:

- ADCCLK: 45 MHz, unchanged from the example project
- Overlap mode and non-overlap mode
- Different ACQPS settings

As shown in the attached graphs, the VREFLO conversion results vary depending on the overlap/non-overlap setting and the ACQPS value.

Comparison of VREFLO Conversion Results by ACQPS in Overlap and Non-Overlap Modes.png

I believe that this behavior may be related to the offset-error characteristics shown in Figures 2 and 3 of the application report "C2000™ ADC (Type-3) Performance Versus ACQPS," particularly the following statements:

"Each ACQPS setting needs to be trimmed differently, as each of the values
leads to a different offset error under the same system conditions."

"If this is done in an application, then each channel should be calibrated separately."

However, in the Example_2806xAdcSoc example project, AdcOffsetSelfCal() is executed in overlap mode,
and the ADC is then configured for non-overlap mode.

If the application performs ADC conversions in non-overlap mode, could you please clarify the following points?

1. Should AdcOffsetSelfCal() also be executed in non-overlap mode?

2. Should the ACQPS value used by AdcOffsetSelfCal() match the ACQPS value used by the application?

 

I also have a question about the discrepancies between the offset-error trends shown in Figures 2 and 3 and the VREFLO conversion results measured in my tests.
Comparison of Figure 2 and Measured VREFLO Results at ACQPS = 23 and 35.png
Comparison of Figure 3 and Measured VREFLO Results at ACQPS = 9 and 14.png
In Figure 2, at 45 MHz in overlap mode, the offset error at ACQPS = 35 is larger than that at ACQPS = 23.
Therefore, I expected to observe a corresponding difference in the measured VREFLO results.
However, the measured average VREFLO results were as follows:
- ACQPS = 23: 72.7 LSB
- ACQPS = 35: 73.8 LSB
The measured difference was only 1.1 LSB, which appears to be smaller than the difference indicated in Figure 2.
 
On the other hand, in Figure 3, at 45 MHz in non-overlap mode, the offset errors at ACQPS = 9 and ACQPS = 14 appear to be approximately the same.
Therefore, I expected the measured VREFLO results to be similar.
However, the measured average VREFLO results were as follows:
- ACQPS = 9  : 93.4 LSB
- ACQPS = 14: 73.7 LSB
The measured difference was 19.7 LSB, although Figure 3 appears to show similar offset errors for these two ACQPS settings.
 
Could you please clarify why the measured VREFLO results do not follow the offset-error trends shown in Figures 2 and 3?
 
 
I also have a question about the behavior observed when using non-valid ACQPS values.
Overlap Mode VREFLO Results for Non-Valid ACQPS Values.png
For example, when ACQPS was set to 18, 31, or 45 in overlap mode,
the VREFLO conversion results periodically alternated between approximately 49 to 50 LSB and approximately 98 to 100 LSB, as shown in the attached graph.
This does not appear to be random noise. Instead, the ADC appears to alternate between two distinct conversion-result levels.
 
Could you please explain why non-valid ACQPS settings can cause this type of periodic behavior in the conversion results?

Thank you.
  • +1
    TI__Genius 9770 points

    Hello,

    1. For both calibration questions, I recommend matching the application’s ADC clock, overlap/non-overlap mode, and valid ACQPS setting. For your application, configure non-overlap mode before calibration, while the ADC is idle. The F2806x errata specifies performing AdcOffsetSelfCal() after Device_cal() and ADC configuration.
    2. The report focuses on F2803x devices; although its guidance applies to Type-3 ADCs, these curves should not be treated as exact predictions for an individual F28065. If your plots capture this stage, the readings include that intentional positive offset. The calibration then writes 80 − average to ADCOFFTRIM. This explains why intermediate readings can be near 80 LSB, but the 19.7 LSB difference still needs investigation.
    3. At 45 MHz, ACQPS values 18, 31, and 45 fall outside the valid overlap-mode ranges in Table 1. These settings can produce errors beyond the specified ADC performance, so they should be avoided.

    Best regards,
    Masoud 

  • 0 in reply to Masoud Farhadi
    Prodigy 10 points

    Thank you for your support.

    We found that the issue could be resolved when AdcOffsetSelfCal() was executed using the same ACQPS setting and overlap mode as the application.

    We will therefore proceed with this configuration.

    Thank you for your assistance.