Part Number: TMS320F28P650DK
Hello TI Team,
I am working on a dual-CPU application using the TMS320F28P650DK6 MCU and the TI C2000 MotorControl SDK.
I have a MotorControl SDK application that runs correctly when executed on CPU1, but the same application does not behave correctly when executed on CPU2.
MCU / Software
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MCU: TMS320F28P650DK6
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Software: TI C2000 MotorControl SDK
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IDE: Code Composer Studio
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CPU1 + CPU2 dual-core application
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Motor-control application using ePWM, ADC, and control ISR
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Both CPUs are configured with the required peripheral clocks.
What I have observed
The same motor-control code works correctly on CPU1.
When I move/run the same control application on CPU2, the motor-control behavior is different.
For example, at approximately 20 Hz speed reference:
| Parameter | CPU1 | CPU2 |
|---|---|---|
| Speed reference | ~20 Hz | ~20 Hz |
| DC bus voltage | ~42 V | ~42 V |
speed_Hz feedback |
~21.19 Hz | ~0.0388 Hz |
Therefore, the CPU2 application is executing, but the motor-control feedback/control behavior is not equivalent to CPU1.
CPU1 / CPU2 clock observation
I compared the CPU1 and CPU2 device.h and device.c configurations.
Both CPUs are configured for:
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20 MHz XTAL
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200 MHz SYSCLK
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50 MHz LSPCLK
The CPU1 code boots CPU2 using Device_bootCPU2().
I also tested a simple LED toggle on both CPUs.
The LEDs do not turn ON/OFF at exactly the same instant, but the time offset remains approximately constant for every cycle.
Therefore, I believe this is primarily a startup/phase offset rather than a continuously accumulating CPU clock-frequency difference.
Peripheral configuration
I have enabled/configured the peripherals required by the CPU2 application, including the peripherals used by the MotorControl SDK application.
The Device_enableAllPeripherals() implementation is also present on CPU2.
I have therefore not intentionally left the required ePWM/ADC/peripheral clock disabled on CPU2.
CPU2 boot sequence
CPU1 releases CPU2 from reset using:
void Device_bootCPU2(uint32_t bootmode)
{
IPC_setBootMode(IPC_CPU1_L_CPU2_R,
(BOOT_KEY | bootmode));
IPC_setFlagLtoR(IPC_CPU1_L_CPU2_R, IPC_FLAG0);
SysCtl_controlCPU2Reset(SYSCTL_CORE_DEACTIVE);
while(SysCtl_isCPU2Reset() == 0x1U);
}
CPU2 successfully starts executing code, so CPU2 is not simply remaining in reset.
My main question
What are the CPU1-specific dependencies in the TI C2000 MotorControl SDK that could cause the same motor-control application to work on CPU1 but behave differently when executed on CPU2?
In particular, could you please advise what I should check regarding:
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ePWM ownership between CPU1 and CPU2
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ADC ownership/configuration
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ePWM → ADC SOC synchronization
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CPU2 interrupt configuration and vector table
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Motor-control ISR execution rate
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CPU timer / system clock dependencies
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CLA or other accelerator dependencies
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Shared RAM / MSGRAM / IPC configuration
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Peripheral access or ownership restrictions between CPU1 and CPU2
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Any MotorControl SDK modules that assume execution on CPU1
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Any CPU1-specific initialization required before the MotorControl SDK can run on CPU2
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Whether ePWM time-base synchronization needs to be explicitly configured between CPU1 and CPU2
Additional question about CPU synchronization
Since CPU2 is released from reset by CPU1, should I expect a fixed phase offset between CPU1 and CPU2 execution?
If so, is there any recommended TI mechanism for synchronizing the motor-control timing/ISR between CPU1 and CPU2, rather than simply synchronizing the software startup?
I can provide the complete CPU1 and CPU2 project files, linker command files, device.c/.h, ePWM/ADC configuration, and MotorControl SDK source if required.
I would particularly appreciate guidance on how to identify why the MotorControl SDK control loop produces correct speed feedback on CPU1 but almost zero speed feedback on CPU2.
Thank you.