Part Number: TMDSCNCD28388D
Other Parts Discussed in Thread: TMS320F28388D, C2000WARE
Hello,
I'm seeing intermittent SCI data when the SCI-D RX pin is left unconnected, even though only SCI-D TX is being used for the data link.
SETUP
- Device: TMS320F28388D, SCI code running on CPU1
- Software: C2000Ware 4.03, CCS 12.2
- SCI-D TX GPIO104
- SCI-D RX GPIO77
- Baud: 2.5Mbps, FIFO: no post transmit FIFO and receive FIFO interrupt level is 5.
- GPIO config for SCI-D rx and tx are both asynchronous.
- Board B decodes the data received on its SCI-D RX and outputs it on DAC channels for monitoring
CONFIGURATION 1 - WORKS
Board A Board B
SCI-D TX ----------> SCI-D RX
SCI-D RX <---------- SCI-D TX
CONFIGURATION 2 - INTERMITTENT DATA AT BOARD B SCI-D RX
Board A Board B
SCI-D TX ----------> SCI-D RX
SCI-C RX <---------- SCI-D TX
SCI-D RX (not connected, floating)
The Board A SCI-D TX -> Board B SCI-D RX connection is identical in both configurations. The only difference is that Board A's SCI-D RX is left unconnected and Board B's TX goes to Board A's SCI-C RX instead. Board A's SCI-D RX is still initialized and enabled in configuration 2.
SYMPTOM
- Configuration 1: data received by Board B is clean. The DAC outputs show continuous signal waveform
- Configuration 2: data received by Board B becomes intermittent
QUESTIONS
1. Is there any known erratum or documented behavior on the F2838x where RX error conditions (break detect, framing error, overrun) caused by a floating RX pin affect the TX operation of the same SCI module?
2. What is TI's recommended configuration for an SCI RX pin that is left unconnected?
3. What is the recommended way to handle SCI RX errors without disturbing an ongoing TX? For example, is SCI_performSoftwareReset() or an RX FIFO reset expected to abort a TX frame in progress?
4. Is there anything else you would suggest checking in this situation?
Thank you.
