TMS320F280039C: Synchronization issue between EPWM3 (SYNC OUT) and EPWM1(SYNC IN)

Hi Hojoong,

With TBCTL[PHSEN] = 0, EPWM1's time-base counter never loads TBPHS from the SYNC pulse — PHSEN is the enable bit that allows the EPWMxSYNCI event to actually load the phase register into the active counter 1. The TRM confirms this explicitly:

"The SYNCEVT signal is only propagated through when PHSEN is SET." 1

So, with PHSEN=0, EPWM1's counter free-runs independently once started. Even if both EPWM3 and EPWM1 are configured for the exact same TBPRD, any sub-cycle difference in start time, clock domain crossing delay, or rounding will cause the two counters to drift apart over time — this drift is exactly the "jitter" you're observing. Global load (GLDCTL/GLDCFG) only controls when shadow→active register transfers happen for registers like TBPRD/CMPx — it does not re-synchronize the time-base counter itself. Only the SYNCI→TBPHS load (gated by PHSEN) does that.

Why re-enabling PHSEN fixes it

When PHSEN=1, every SYNCOUT pulse from EPWM3 forces EPWM1's counter to reload TBPHS, continuously correcting any accumulated drift. This is the intended mechanism for maintaining tight phase lock between a master and slave ePWM — not an optional feature you can bypass with global load alone.

Your GLDCTL2LINK/GLDMODE override

EPwm1Regs.EPWMXLINK.bit.GLDCTL2LINK = 2U;  // EPWM1 GLDCTL2 follows EPWM3
EPwm1Regs.GLDCTL.bit.GLDMODE = 4U;         // Global load on EPWM3 SYNC

This setup governs register content updates (e.g., simultaneous CMPA/TBPRD loading across EPWM3 and EPWM1), as described in the global load documentation 2 3. It is a complementary mechanism to time-base sync, but it is not a substitute for PHSEN when your goal is counter-level phase alignment. This is likely why you see "most" jitter removed by PHSEN=1 but believe global load alone should be sufficient — the two features solve different problems:

Recommendation

Per the TRM and TI reference designs (e.g., TIDA-00961 pattern) 4, if tight phase lock between EPWM3 (master) and EPWM1 (slave) is required, keep TBCTL[PHSEN] = 1 on EPWM1 so the SYNCI event continuously corrects the counter. Use global load/link registers for your register-content synchronization needs (CMPA, TBPRD, etc.), but don't rely on them for counter phase correction.

1. TMS320F28003x TRM — Global Load (Section 20.4.7)
2. Global Load and One Shot Load Mode — SPRACY1
3. Safe and Optimized PWM Updates — SPRACN0F
4. TIDA-00961 Global Load/One-Shot Example — SPRACY1

Best Regards,

Zackary Fleenor