C2000™︎ microcontrollers

C2000 microcontrollers forum

State Resolved
Replies 3 replies
Subscribers 83 subscribers
Views 102 views
Users 0 members are here

Support feedback

Options

Options

Related

TMS320F28379D: CLB Tile and CLB Register Clock

Hitesh Kumar

Prodigy 120 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: SYSCONFIG

Based on the uploaded image, I have the following questions:

In the TRM, the CLB Register Clock is shown as connected to SYSCLK; however, in the clock tree, it appears to be connected to PLLCLK. Could you please explain this discrepancy?
What is the maximum supported frequency for the CLB Tile clock and the CLB Register clock?
Where are the CLBCLKDIV and TILECLKDIV registers located?

0 Joe Prushing 8 days ago

TI__Genius 17451 points

Our subject matter expert for this topic is out of office today. You can expect a reply tomorrow. Thank you for your patience.

+1 Aishwarya Rajesh 6 days ago

TI__Mastermind 21665 points

Hi Hitesh,

1. Please follow the TRM diagram for the correct implementation. I've filed a Jira for the SysConfig Clocktree Tool to be reviewed.

2/3. The CLBCLKDIV and TILECLKDIV are not present on this device. The maximum CLB clock frequency is 100 MHz as listed in the TRM.

Thank you for bringing this to our attention.

Best Regards,

Aishwarya

0 Hitesh Kumar 3 hours ago in reply to Aishwarya Rajesh

Prodigy 120 points

Thank you, TI Team, for the clarification. I appreciate your prompt support.