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TMS320F28027: ADC EOC interrupt triggered twice unepxectedly

Hang Yang
Expert 4256 points

Part Number: TMS320F28027

Hi Experts,

My customer is using ADC EOC interrupt. However, they obsered the interrupt is triggered twice unexpectly.

image.png

The trigger chains is like:

 ePWM zero (also attached with a pull-up AQ) -> ADC SOC0,1,2 0 -> ADC EOC2 (ECO0,1 not used) -> Early interrupt.

You may see the rising edge is followed by two GPIO sikes, which marks the interrupt enter and exit. It's expected be only one spike per rising edge.

One thing is that the simutaious sampling is enabled, so the SCO0 and SOC1 are binded. However, the ePWM is still configured to trigger SOC0 and SOC1, which means that SOC0 and SOC1 would be triggered twice. Disalbing the simutainous sampling, or removing SOC1 trigger would elmiate the extra interrupt. Also, switch from early interrupt to late interrupt would also elimiate the extra interrupt.

However, I can't connect the above observation to the issue since the interrupt are triggered by EOC2, and the above experiment only inpacts SOC/EOC 0 and 1.

I attached the register dump when the issue happens.test2610211636.txt . You may help checking the trigger configurations.

Regards,

Hang

  • 0
    TI__Genius 9990 points

    Thanks for your patient here. We'll reply soon.

    Best Regards,

    Masoud

  • 0 in reply to Masoud Farhadi
    TI__Genius 9990 points

    Hi Hang,

    The register dump your customer provided clarifies exactly why the ADC interrupt is triggering twice unexpectedly. The root cause is a combination of simultaneous sampling mode, overlapping ePWM SOC triggers, and an unhandled ADC Interrupt Overflow condition.

    Looking at your .txt attachment, we can look directly at the ADC configuration:
    • ADC_ADCSAMPLEMODE = 0x0001: Simultaneous sampling is explicitly enabled for the SOC0 and SOC1 pair. In this mode, triggering SOC0 automatically triggers both SOC0 and SOC1 to sample concurrently on their respective A/B channels.
    • ADC_INTSEL1N2 = 0x0062: This means ADCINT1 is enabled (Bit 5 = 1), and it is explicitly mapped to EOC2 (INTSEL = 2, Bits 4:0 = 00010).
    • ADC_ADCINTOVF = 0x0001: This is a critical clue. The ADCINT1 overflow flag is set. This proves that a second ADC interrupt event is being generated before the CPU has a chance to clear the primary flag.
    • ADC_ADCSOCFLG1 = 0x07C0 and ADC_ADCSOCOVF1 = 0x0FC0: Channels 6, 7, 8, 9, 10, and 11 have pending triggers and severe overflow flags active. This indicates high peripheral trigger congestion or back-to-back triggers hitting the ADC wrapper.

    When simultaneous sampling is active on the Piccolo architecture, triggering SOC0 samples both CH0 and CH1 simultaneously. However, your customer's hardware configuration is issuing two separate hardware trigger pulses at the exact same instant (ePWM Zero is hitting both the SOC0 configuration and the SOC1 configuration).
    Because Early Interrupt mode is enabled (ADCCTL1.INTPULSEPOS = 0, seen in ADC_ADCCTL1 = 0x47E0), the ADCINT1 flag trips at the beginning of the conversion window rather than at the end.
    1. Trigger Phase 1: ePWM zero fires. SOC0 is evaluated. Because simultaneous mode is active, the ADC immediately schedules conversions for CH0 and CH1. SOC2 follows sequentially. As soon as SOC2 enters its conversion phase, EOC2 trips early, and the first CPU interrupt executes.
    2. Trigger Phase 2: Because ePWM zero was also routed to fire SOC1 independently, a second, delayed hardware trigger event hits the sequencer wrapper while the first set of conversions is still finalizing. This causes the sequencer to execute a back-to-back conversion loop.
    3. The Double Trip: SOC2 is processed a second time in this shadow loop. EOC2 fires a second time. Because the CPU is still inside or just exiting the first Interrupt Service Routine (ISR) and hasn't cleared the flag before this second edge arrives, the hardware sets the ADCINTOVF flag. As soon as the CPU exits the first ISR and clears the PIE ACK, the pending second edge immediately forces the CPU back into the ISR, creating the double GPIO spike you see on the scope.

    The customer should keep simultaneous sampling enabled but must remove the redundant ePWM trigger channel connection.

    Best Regards,
    Masoud Farhadi