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TMS320F28P650DK: decoupling caps requirement

YY
Expert 4070 points

Part Number: TMS320F28P650DK

Hello BU,

My customer is asking about decoupling capacitance.

The datasheet states that the total decoupling capacitance for the VDD terminals should be at least approximately 20uF.
However, the operating conditions for the power management module specify that the typical value for CVDD (Total) when using the internal VREG is 10uF or 22uF.
The "20uF" instruction seems to imply a minimum requirement, yet the "10uF or 22uF" is listed as a typical value under specific conditions.
Since there are five VDD terminals, I interpret the requirement as follows: 22uF / 5 terminals = 4.4uF (effective capacitance) approx 4.7uF per terminal as a recommended value.
Is this understanding correct if the internal regulator is configured?
Additionally, what is the maximum allowable value for CVDD?
 
Best Regards,
Yuki
  • +1
    TI__Guru* 86550 points

    Yuki,

    The background here is that we can support a total value within that range, where typical assumes +/-20% tolerant cap.  

    What you have listed will work, i.e. 4.4uF on each VDD pin.  The DS does provided for an alternate option if that is more attractive from a system POV:

    I would recommend to stay within the 22uF +20% as a system max for CVDD; while bigger cap values may work, it will increase the power up time of the VDD rail supplied from the internal regulator.

    Best,
    Matthew