McBSP is SPI slave over 28069

Michi M

Intellectual 490 points

Hi all,

I have 28069, McBSP as a SPI slave, data-clock-sync provided by FPGA.

I set up the peripheral according to spruh18c.

Still I see that DRR1 and DRR2 are empty.

Is there anything else I forgot?

Thanks in advance.

    McbspaRegs.SPCR2.all=0x0000;       // Reset FS generator, sample rate generator & transmitter
   McbspaRegs.SPCR1.all=0x0000;       // Reset Receiver, Right justify word
    McbspaRegs.SPCR1.bit.CLKSTP = 2;   // Together with CLKXP/CLKRP determines clocking scheme
   McbspaRegs.PCR.bit.CLKXP = 0;             // CPOL = 0, CPHA = 0 rising edge no delay
   McbspaRegs.PCR.bit.CLKRP = 0;
// McbspaRegs.SPCR1.bit.DLB = 1;             // Enable loopback mode for test. Comment out for normal McBSP transfer mode.
    McbspaRegs.MFFINT.all=0x0;                    // Disable all interrupts
   McbspaRegs.RCR2.all=0x0;              // Single-phase frame, 1 word/frame, No companding (Receive)
   McbspaRegs.RCR1.all=0x0;
   McbspaRegs.XCR2.all=0x0;                       // Single-phase frame, 1 word/frame, No companding (Transmit)
   McbspaRegs.XCR1.all=0x0;
    McbspaRegs.PCR.bit.FSXM = 0;          //1;   // FSX generated internally, FSR derived from an external source
   McbspaRegs.PCR.bit.FSXP = 1;
   McbspaRegs.PCR.bit.CLKXM = 0;       //1;   // CLKX generated internally, CLKR derived from an external source
   McbspaRegs.PCR.bit.SCLKME = 0;
   McbspaRegs.SRGR2.bit.CLKSM = 1;       // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
    McbspaRegs.RCR2.bit.RDATDLY = 0;      // FSX setup time 1 in master mode. 0 for slave mode (Receive)
    McbspaRegs.XCR2.bit.XDATDLY = 0;   // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
    McbspaRegs.SRGR2.bit.FPER = 31;       // FPER = 32 CLKG periods
   McbspaRegs.SRGR1.bit.FWID = 0;           // Frame Width = 1 CLKG period
    McbspaRegs.SRGR1.bit.CLKGDV = 1;   // CLKG frequency = LSPCLK/(CLKGDV+1)
    delay_loop();                                                   // Wait at least 2 SRG clock cycles
   McbspaRegs.SPCR2.bit.GRST=1;        // Enable the sample rate generator
   clkg_delay_loop();                                         // Wait at least 2 CLKG cycles
   McbspaRegs.SPCR2.bit.XRST=1;       // Release TX from Reset
   McbspaRegs.SPCR1.bit.RRST=1;          // Release RX from Reset
   McbspaRegs.SPCR2.bit.FRST=1;            // Frame Sync Generator reset
   InitMcbspa16bit();

over 13 years ago

0 Kris Parrent over 13 years ago

TI__Genius 15260 points

Hello,

Could you post your IO configuration for the McBSP as well? Thanks,

Kris

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

void InitMcbspaGpio(void)
{
   EALLOW;

/* Configure McBSP-A pins using GPIO regs*/
// This specifies which of the possible GPIO pins will be McBSP functional pins.
// Comment out other unwanted lines.

   GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2;    // GPIO20 is MDXA pin
   GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2;    // GPIO21 is MDRA pin
   GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2;    // GPIO22 is MCLKXA pin
   GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 2;    // GPIO53 is MFSXA pin

// GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1;    // GPIO58 is MCLKRA pin
//   GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 1;    // GPIO44 is MFSRA pin

//   GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 2;    // GPIO50 is MDXA pin
//   GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 2;    // GPIO51 is MDRA pin
//   GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 2;    // GPIO52 is MCLKXA pin
// GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2;    // GPIO23 is MFSXA pin

/* Enable internal pull-up for the selected pins */
// Pull-ups can be enabled or disabled by the user.
// This will enable the pullups for the specified pins.
// Comment out other unwanted lines.

   GpioCtrlRegs.GPAPUD.bit.GPIO20 = 0;       // Enable pull-up on GPIO20 (MDXA)
   GpioCtrlRegs.GPAPUD.bit.GPIO21 = 0;       // Enable pull-up on GPIO21 (MDRA)
   GpioCtrlRegs.GPAPUD.bit.GPIO22 = 0;       // Enable pull-up on GPIO22 (MCLKXA)
   GpioCtrlRegs.GPBPUD.bit.GPIO53 = 0;     // Enable pull-up on GPIO53 (MFSXA)

//   GpioCtrlRegs.GPBPUD.bit.GPIO58 = 0;       // Enable pull-up on GPIO58 (MCLKRA)
//   GpioCtrlRegs.GPAPUD.bit.GPIO23 = 0;       // Enable pull-up on GPIO23 (MFSXA)
//   GpioCtrlRegs.GPBPUD.bit.GPIO44 = 0;       // Enable pull-up on GPIO44 (MFSRA)
//   GpioCtrlRegs.GPBPUD.bit.GPIO50 = 0;     // Enable pull-up on GPIO50 (MDXA)
//   GpioCtrlRegs.GPBPUD.bit.GPIO51 = 0;     // Enable pull-up on GPIO51 (MDRA)
//   GpioCtrlRegs.GPBPUD.bit.GPIO52 = 0;     // Enable pull-up on GPIO52 (MCLKXA)

/* Set qualification for selected input pins to asynch only */
// This will select asynch (no qualification) for the selected pins.
// Comment out other unwanted lines.

   GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3;   // Asynch input GPIO21 (MDRA)
   GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3;   // Asynch input GPIO22 (MCLKXA)
   GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3;    // Asynch input GPIO53 (MFSXA)

//   GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3;    // Asynch input GPIO58 (MCLKRA)
//   GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3;   // Asynch input GPIO23 (MFSXA)
//   GpioCtrlRegs.GPBQSEL1.bit.GPIO44 = 3;    // Asynch input GPIO44 (MFSRA)
//   GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3;    // Asynch input GPIO51 (MDRA)
//   GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3;    // Asynch input GPIO52 (MCLKXA)

    EDIS;
}

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

Can you also confirm your connections from the FPGA are connected as shown:

If so, what frequency is your FPGA transmitting at? Do you have the clock to the McBSP enabled in one of the SysCtrlRegs.PCLKCR registers?

Kris

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

Hi Kris,

Thanks for your advices, now I can see data on DRR1 !

Now:

DRR1 is written, RRDY changes to 1.
if i read DRR1 in background, RRDY is correctly cleared (RINTM=0)

The problem is that MRINTA interrupt is not called.

I have:

----------------------------------------------------------------------------------------

SysCtrlRegs.PCLKCR0.bit.MCBSPAENCLK=1; // McBSP-A

----------------------------------------------------------------------------------------

#define G65PL 1 // MRINTA (McBSP-A)

----------------------------------------------------------------------------------------

#define INT6PL 4 // Group6 Interrupts (PIEIER6)

----------------------------------------------------------------------------------------
#if (G65PL != 0)
interrupt void MRINTA_ISR(void)     // McBSP-A
{
   // Set interrupt priority:
   volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER6.all;
   IER |= M_INT6;
   IER   &= MINT6;                       // Set "global" priority
   PieCtrlRegs.PIEIER6.all &= MG65;   // Set "group" priority
   PieCtrlRegs.PIEACK.all = 0xFFFF;   // Enable PIE interrupts
   EINT;

   // Insert ISR Code here.......

    Read_data_from_DRR1();

//   asm("      NOP");

   // Restore registers saved:
   DINT;
   PieCtrlRegs.PIEIER6.all = TempPIEIER;

    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
//    asm ("      ESTOP0");
//    for(;;);
}
#endif

----------------------------------------------------------------------------------------

What did I forget?

Thanks,

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

Great news! Have you enabled the McBSP interrupt in the PIE?

If you look at pg 170 of the f28069 TRM (http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=spruh18c&fileType=pdf), you will see that the McBSP RX interrupt corresponds to 6.5 in the PIE table. This is should be done in prior to receiving any data on the McBSP.

PieCtrlRegs.PIEIER6.bit.INTx5 = 1; // Enable 6.5 in PIE

IER |= M6; // Enable Row 6 in PIE

EINT; // Enable global interrupts

I see in your code you are doing:

define INT6PL 4 // Group6 Interrupts (PIEIER6)

Can you explain what this 4 is for? You also do not want to use the IER commands inside the interrupts. This is just to enable the vector in the PIE. So if it reaches this interrupt, you know they are already enabled. I think if you take your PIE initialization code out of the ISR (except for the ACK, this is required to receive more interrupts by clearing the flag, NOT enable the vector) it may work.

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

Hello,

I went few steps further, now the interrupt works properly thanks to

McbspaRegs.MFFINT.bit.RINT = 1;

during initialization.

---------

The last ( I hope) problem is that i loose the first bit of the 16bits-frame (FPGA writes 0x1000, DSP shifts on the left and reads 0x2000)

----------------------------------------------------------------------------

void InitMcbspa(void)
{
// McBSP-A register settings

   McbspaRegs.SPCR2.all=0x0000;       // Reset FS generator, sample rate generator & transmitter
   McbspaRegs.SPCR1.all=0x0000;       // Reset Receiver, Right justify word

   McbspaRegs.SPCR1.bit.CLKSTP = 2;   // Together with CLKXP/CLKRP determines clocking scheme
   McbspaRegs.SPCR2.bit.FREE = 1;
   McbspaRegs.PCR.bit.CLKXP = 0;       // CPOL = 0, CPHA = 0 rising edge no delay
   McbspaRegs.PCR.bit.CLKRP = 0;

   McbspaRegs.PCR.bit.FSXP = 1;       // Frame Sync    1 active low 0 active high
   McbspaRegs.PCR.bit.FSRP = 1;       // Frame Sync    1 active low 0 active high

//   McbspaRegs.SPCR1.bit.DLB = 1;       // Enable loopback mode for test. Comment out for normal McBSP transfer mode.

   McbspaRegs.MFFINT.all=0x0;           // Disable all interrupts
   McbspaRegs.RCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Receive)
   McbspaRegs.RCR1.all=0x0;
   McbspaRegs.XCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Transmit)
   McbspaRegs.XCR1.all=0x0;

   McbspaRegs.PCR.bit.FSXM = 0;       //1;   // FSX generated internally, FSR derived from an external source
   McbspaRegs.PCR.bit.FSXP = 1;
   McbspaRegs.PCR.bit.CLKXM = 0;       //1;   // CLKX generated internally, CLKR derived from an external source
   McbspaRegs.PCR.bit.SCLKME = 0;
   McbspaRegs.SRGR2.bit.CLKSM = 1;       // CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
    McbspaRegs.RCR2.bit.RDATDLY = 0 ;   // FSX setup time 1 in master mode. 0 for slave mode (Receive)
    McbspaRegs.XCR2.bit.XDATDLY = 0;   // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

//   McbspaRegs.SRGR2.all=   0x2000;          // CLKSM=1, FPER = 1 CLKG periods
//    McbspaRegs.SRGR1.all=   0x0001;        // Frame Width = 1 CLKG period, CLKGDV=1 for slave

//   McbspaRegs.SRGR2.bit.FPER = 31;       // FPER = 32 CLKG periods
//   McbspaRegs.SRGR1.bit.FWID = 0;       // Frame Width = 1 CLKG period

//   McbspaRegs.SRGR1.bit.CLKGDV = 1;   // CLKG frequency = LSPCLK/(CLKGDV+1)

   delay_loop();                       // Wait at least 2 SRG clock cycles
   McbspaRegs.SPCR2.bit.GRST=1;        // Enable the sample rate generator
   clkg_delay_loop();                  // Wait at least 2 CLKG cycles
   McbspaRegs.SPCR2.bit.XRST=1;        // Release TX from Reset
   McbspaRegs.SPCR1.bit.RRST=1;        // Release RX from Reset
   McbspaRegs.SPCR2.bit.FRST=1;        // Frame Sync Generator reset
   InitMcbspa16bit();

   McbspaRegs.MFFINT.bit.RINT = 1;
    PieCtrlRegs.PIEIER6.bit.INTx5 = 1;   // Enable 6.5 in PIE
   IER |= M_INT6;                     // Enable Row 6 in PIE
}
----------------------------------------------------------------------------

Thanks for your help.

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

Great!

Two suggestions to look at:

1) Make sure the FSR signal is configured to come from the correct source. If the FPGA is sending the FSR signal, make sure your program is looking for an external signal.

2) Make sure the data delay configuration between the FSR and the data is configured to what the FPGA is actually sending. See "Set the Receive Data Delay" on pg 971 for more details. It looks like your data delay may be off by one bit.

Kris

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

Hello,

McbspaRegs.SPCR1.bit.CLKSTP = 2; // the mcbsp is slave, it follows the external FS and CLK
McbspaRegs.RCR2.bit.RDATDLY = 0; // there is no receive data delay

-------------------------------------------------------------------------------------------------------------------------

void InitMcbspa(void)
{
    McbspaRegs.SPCR2.all=0x0000;       // Reset FS generator, sample rate generator & transmitter
   McbspaRegs.SPCR1.all=0x0000;       // Reset Receiver, Right justify word

   McbspaRegs.SPCR1.bit.CLKSTP = 2;

   McbspaRegs.PCR.bit.CLKXM = 0;
   McbspaRegs.PCR.bit.CLKXP = 1;

    McbspaRegs.PCR.bit.CLKRP = 0;

   McbspaRegs.MFFINT.all=0x0;           // Disable all interrupts

   McbspaRegs.RCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Receive)
   McbspaRegs.RCR1.all=0x0;
   McbspaRegs.XCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Transmit)
   McbspaRegs.XCR1.all=0x0;

   McbspaRegs.PCR.bit.SCLKME = 0;
   McbspaRegs.SRGR2.bit.CLKSM = 1;

   McbspaRegs.SRGR1.bit.CLKGDV = 1;   // CLKG frequency = LSPCLK/(CLKGDV+1)

   McbspaRegs.PCR.bit.FSXM = 0;
   McbspaRegs.PCR.bit.FSXP = 1;

    McbspaRegs.RCR2.bit.RDATDLY = 0 ;   // FSX setup time 1 in master mode. 0 for slave mode (Receive)
    McbspaRegs.XCR2.bit.XDATDLY = 0;   // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

   delay_loop();                          // Wait at least 2 SRG clock cycles
   McbspaRegs.SPCR2.bit.GRST=1;        // Enable the sample rate generator
   clkg_delay_loop();                                 // Wait at least 2 CLKG cycles
   McbspaRegs.SPCR2.bit.XRST=1;        // Release TX from Reset
   McbspaRegs.SPCR1.bit.RRST=1;        // Release RX from Reset
   McbspaRegs.SPCR2.bit.FRST=1;        // Frame Sync Generator reset
   InitMcbspa16bit();

   McbspaRegs.MFFINT.bit.RINT = 1;
    PieCtrlRegs.PIEIER6.bit.INTx5 = 1;   // Enable 6.5 in PIE
   IER |= M_INT6;                     // Enable Row 6 in PIE
}

-------------------------------------------------------------------------------------------------------------------------

Now :

the data is still left-shifted, i always loose the MSB (the first), i played with polarities of clock and FS with no result.
i often receive corrupted data, i changed the input qualification from 3 to 1 but it didnt help.

Thanks for your help!

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

My apologies, I forgot this was in SPI mode. If you're 100% sure you have the clock polarities and phase configured correctly, then we need to look at what frequency the FPGA is transmitting. Please note that the TI description of clock phase differs from that of many manufacturers, so take a close look at the waveform diagram.

You want to make sure your IOs are configured for asynchronous operation as well.

Kris

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

With input clock on MCLKX, i expect the following to be correct (see page 935)

    McbspaRegs.PCR.bit.SCLKME = 1;
   McbspaRegs.SRGR2.bit.CLKSM = 1;
    McbspaRegs.SRGR1.bit.CLKGDV = 0;//1;   // CLKG frequency = LSPCLK/(CLKGDV+1)

but in this case i have no data on DRR1.

It only works if

McbspaRegs.PCR.bit.SCLKME = 0;

using internal clock.

SCLKSME = 1 should let my external clock go through..... isn't it?

Thanks

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

CLKGDV=0 is an invalid value. The maximum value for CLKGDV is LSPCLK (or whatever source clock) / 2

Let's fix that and then see if the problems clear up.

SCLKME needs to be 0 for SPI mode. See page 962 of the TRM for slave setup requirements.

Kris

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

Hello,

Communication works -almost- fine in both Tx and Rx with the following configuration

-------------------------------------------------------------------------------------------------------------------------------------
void InitMcbspa(void)
{
// McBSP-A register settings

   McbspaRegs.SPCR2.all=0x0000;
   McbspaRegs.SPCR1.all=0x0000;

   McbspaRegs.SPCR2.bit.XINTM=2;

   McbspaRegs.SPCR1.bit.CLKSTP = 2;

   McbspaRegs.PCR.bit.CLKXM = 0;
   McbspaRegs.PCR.bit.CLKXP = 1;

    McbspaRegs.PCR.bit.CLKRP = 0;

    McbspaRegs.MFFINT.all=0x0;

   McbspaRegs.RCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Receive)
   McbspaRegs.RCR1.all=0x0;
   McbspaRegs.XCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Transmit)
   McbspaRegs.XCR1.all=0x0;

    McbspaRegs.SPCR2.bit.FREE = 1;

   McbspaRegs.PCR.bit.SCLKME = 0;
   McbspaRegs.SRGR2.bit.CLKSM = 1;

   McbspaRegs.SRGR1.bit.CLKGDV = 1;   // CLKG frequency = LSPCLK/(CLKGDV+1)

   McbspaRegs.PCR.bit.FSXM = 0;
   McbspaRegs.PCR.bit.FSXP = 1;

    McbspaRegs.RCR2.bit.RDATDLY = 0 ;   // FSX setup time 1 in master mode. 0 for slave mode (Receive)
    McbspaRegs.XCR2.bit.XDATDLY = 0;   // FSX setup time 1 in master mode. 0 for slave mode (Transmit)

    InitMcbspa32bit();

    delay_loop();
   McbspaRegs.SPCR2.bit.GRST=1;        // Enable the sample rate generator
   clkg_delay_loop();
   McbspaRegs.SPCR2.bit.XRST=1;        // Release TX from Reset
   McbspaRegs.SPCR1.bit.RRST=1;        // Release RX from Reset
   McbspaRegs.SPCR2.bit.FRST=1;        // Frame Sync Generator reset

   McbspaRegs.MFFINT.bit.RINT = 1;
   McbspaRegs.MFFINT.bit.XINT = 1;

   PieCtrlRegs.PIEIER6.bit.INTx5 = 1;   // Enable 6.5 in PIE
   PieCtrlRegs.PIEIER6.bit.INTx6 = 1;   // Enable 6.6 in PIE
   IER |= M_INT6;                     // Enable Row 6 in PIE
}
-------------------------------------------------------------------------------------------------------------------------------------

I see a 1-clock delay in both TX and RX, even if

McbspaRegs.RCR2.bit.RDATDLY = 0;
McbspaRegs.XCR2.bit.XDATDLY = 0;

Are there any other registers influencing the delay?

Thanks,

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

What frequency is the FPGA transmitting at?

What is the value of SysCtrlRegs.LOSPC.LSPCLK?

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

Kris Parrent said:

What frequency is the FPGA transmitting at?

20MHz

What is the value of SysCtrlRegs.LOSPC.LSPCLK?

0

0 Kris Parrent over 13 years ago in reply to Michi M

TI__Genius 15260 points

Hello,

If you look at the datasheet, you will find that 20 MHz is well beyond the capabilities of the McBSP in SPI slave mode on this device (see pg 124, max CLKX = 5 MHz). If you need to go faster I recommend using the SPI module, which is specified to be able to receive at 10 MHz on this device. You can attempt to receive at 20 MHz with it, but we do not guarantee reliability.

Kris

0 Michi M over 13 years ago in reply to Kris Parrent

Intellectual 490 points

I see. The only solution in my case is to set-up mcbsp as spi-master (page 961) because it supports 20Mhz.

Now I have XINTM=0 and i write DXR periodically, but XRDY is always 0 (no XINT request to CPU).

----------------------------------------------------------------------------------------------------------------------------

void InitMcbspa(void)
{
    McbspaRegs.SPCR2.all=0x0000;
   McbspaRegs.SPCR1.all=0x0000;

   McbspaRegs.SPCR2.bit.XINTM=0;   //2;   // Interrupt generation mode

   McbspaRegs.SPCR1.bit.CLKSTP = 2;

   McbspaRegs.PCR.bit.CLKXM = 1;//0;       //1 if master
   McbspaRegs.PCR.bit.CLKXP = 1;
    McbspaRegs.PCR.bit.CLKRP = 0;

    McbspaRegs.MFFINT.all=0x0;           // Disable all interrupts

   McbspaRegs.RCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Receive)
   McbspaRegs.RCR1.all=0x0;
   McbspaRegs.XCR2.all=0x0;           // Single-phase frame, 1 word/frame, No companding (Transmit)
   McbspaRegs.XCR1.all=0x0;

   McbspaRegs.SPCR2.bit.FREE = 1;

   McbspaRegs.PCR.bit.SCLKME = 0;
   McbspaRegs.SRGR2.bit.CLKSM = 1;

   McbspaRegs.SRGR1.bit.CLKGDV = 3;          // 80MHz/4=20MHz clk

   McbspaRegs.PCR.bit.FSXM = 0;
   McbspaRegs.PCR.bit.FSXP = 1;

   McbspaRegs.SRGR2.bit.FSGM = 0;

    McbspaRegs.RCR2.bit.RDATDLY = 1;
    McbspaRegs.XCR2.bit.XDATDLY = 1;

    InitMcbspa32bit();

   delay_loop();
   McbspaRegs.SPCR2.bit.GRST=1;
   clkg_delay_loop();
   McbspaRegs.SPCR2.bit.XRST=1;
   McbspaRegs.SPCR1.bit.RRST=1;
   McbspaRegs.SPCR2.bit.FRST=1;

   McbspaRegs.MFFINT.bit.RINT = 1;
   McbspaRegs.MFFINT.bit.XINT = 1;

   PieCtrlRegs.PIEIER6.bit.INTx5 = 1;
   PieCtrlRegs.PIEIER6.bit.INTx6 = 1;
   IER |= M_INT6;
}

----------------------------------------------------------------------------------------------------------------------------

Thanks for your help.

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McBSP is SPI slave over 28069