320F28335 ADC Noise Problem

Larry,

Did you use the ControlSUITE example as a starting point for your code?  If so, you may want to check the HSPCLK settings as there is a bug in the current example:  http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/t/160912.aspx

Do you know how far off the sampled signal is from the bad reading?  Just want to get an idea of the magnitude of error.

Is it otherwise accurate when not railed?  I assume that you are handling the ADC simultaneous sampling errata behavior.

-Tommy

No, we use Code Composer not ControlSuite.  We havve been using the part for 4 years in several related drives, and do not have the problem on the other PCB layout.  It's not a softwre related issue.

As I said, the signal is usually but not always MAX VALUE - hence the term "railed".  This is not the normal, typical noise from reading to reading.  In fact, the noise floor on our board for general analog I/O is very low, lower than the TI demo card.  However, we are inside a very densly packaged 150kW motor drive, and there is tremendois electrical noise in the vicinity of the board.  There is a continuous Copper shield at CHGND around this card except for cable clearances and the top face, which is open.  The cover comes down and missed the edges of the Copper shield by 1mm all around, so when closed it looks a lot like a shield box.

The OLD layout of the board, and the other scracth layout for a different product, never exhibited this problem.  The new board layout does.

Everything is accurate, and can be calibrated to spec, if you don't happen to catch a noise pulse on that channel.

The behavior becomes more frequent at the inverter power stage CURRENT increases.  In one experiment, up to 300A, not so bad; over that, the disturbance rate increases with load current.

Hi Larry,

you will have to narrow it down. Does it happen also when the power stage is off (maybe the source is not the power stage)? Is it periodic?

Regards, Mitja

It does not happen with PWM off.

It is not synchronouus with the PWM, although is presumably related to some noise event in the inverter power stage. 

But note that all I am changing is the Control Card - the rest of the product is unchanged.  All I THOUGHT I did was change the shape of the Control Card to make it fit better, but this required a significant re-do of the layout around the DSP chip.

As I mentioned, it gets worse as the motor current increases, and is not so much related to bus voltage.

I am hoping that someone has had a similar problem and found out that some bypass capacitor needs to be closer than "X" to the BGA pad or something.

ADC_REFP and ADC_REFM are very close, less than 10mm, and do not go through a via;

ADC_REFIN is tied to a precision 2.048V reference but the bypass cap is quite a distance from the chip, maybe 35mm.  However, this is no worse than either of the previous layouts that work...

What else should I be looking for, physically, around the ADC section of the chip on the layout that could allow noise like this?

I am relatively confident that the signal is NOT present on the actual input, as it can appear at the same magnitude on any channel randomly.

Larry

Larry,

1. Have you done any testing using the internal reference to isolate the possibility of the external reference trace length or similar layout changes as possible sources of the railed readings?
2. Do you have any means of scoping the ADC_REFP, ADC_REFM, ADC_REFIN and ADCINxx lines to monitor for coupling from the strong load current?

Yes, we did try the internal reference.  No improvement.

Realistically, I can put a scope on these signals, and I can even put a scope with floating, isolated input channels on these signals, but there's too much nose to make a useful measurement.  I've tried looking and even using a lot of measurement tricks, it's hard to get a noise pulse measurement that you can believe.

The issue is that the problem happens on only one input at a time, sometimes once a minute, the input changing in a random manner among all the channels.  Some signals are through a mux and analog processing system, some come directly from an off-board sensor, it doesn't matter.

If I put a software filter that ignores ANY ADC reading that differs from the last by >x% OR that is at max readable value, my drive works just fine.  I have a little counter that can sit back and watch these events happen while running.

Scoping the references would be really tough.  Especially if I wanted to minimize the noise pickup.  This is a line interactive AC-AC inverter with line inductors and two inverters all crammed into a little box, so getting at the control card in thsi hardware is really tough.  I do have a standard product using the same board where I can usually duplicate the problems - but not always.

Larry

Larry 

Do you have an extra I/O line that you can toggle with your software detection code? Use it to trigger your oscilloscope(s) to see what is happening on the ADC inputs when the problem occurs. Triggering the Oscilloscope from the software lets you know that the problem really has happened just before the trigger time.

It's worth a try.  We would have to do some snooping or just get lucky, as there are 16 inputs and only a couple scope channels...  We'll see if we can give it a whirl.

Its hard to imagine it coming in an input, but that's still conceivable.  I can try to look at references and analog supply voltages too...

Larry

Do you have more than one PCB available? Is this happening with all PCBs? It might be a mechanical problem? Did you by any chance change the PCB supplier/manufacturer? Just trying to cover all the aspects.

Regards, Mitja

Larry,

I would also take a look at ADCLO and how well it is connected to VSSA(and if there is any ground bounce).  If the ground is bouncing negative it will cause the ADC to read "higher" than normal.

Previous posts have mentioned ADCREFP/M; and you have answered those as well in terms of location of the caps being good; since there was a board re-do can we make sure the caps retained their previous value; i.e. 2.2uF.  If not they may not be buffering the refs like we want them to.

I have observed problems on either REFP/M or ADCLO will cause the railing you have mentioned.  Since internal ref is no better I think we can rule out ADCREFIN.  If the problem is ADCLO it would be coincident with the sample; if the problem is with REFP/M, if this is occurring at any time during the conversion it could mess things up as these are used continuously by the converter.

Finally, I think you mentioned all channels are used, but there is a recommendation to ground out any unused channels; for high noise environments especially.  There is an advisement in the DS if the input on ANY ADC input goes 0.3V above VDDA or 0.3V below VSSA there is potential for that channel to corrupt other channels that are sampling.  This could cause your problem as well and the channels under investigation would appear normal(unused channel is causing this if picking up enough noise via above).

Best,
Matthew