[Concerto]: How to get ADC Data to M3

Andreas and Matthias,

I'm not sure I understand your question.  The ADC1 Result Registers can be accessed by the M3 core at 0x50001600 and ADC2 Result Registers can be accessed by the M3 core at 0x50001640.

Regards,

Ricky

If you are asking for a function from MWare to read the ADC results, we do not currently supply such a function.

Ricky

Hi Andreas,

Do you know how to read that M3 shared register for ADC1 at 0X50001600 in the CCS code.

Please provide detailed commands

Thanks!

Amin

Hi Amin,

we provided the following Files for the M3. Please note that there you also need the C28x programmed.

Adc.h:

/*
 * Adc.h
 *
 *  Created on: 03.04.2012
 *      Author:
 */

#ifndef ADC_H_
#define ADC_H_

typedef unsigned int Uint16;


#define ADRESSE_ADC1 0x50001600  //Startadresse ADC1-Result-Register M3
#define ADRESSE_ADC2 0x50001680  //Startadresse ADC2-Result-Register M3



struct Adc1_Result
{
    unsigned short Ext_Sensor1;     //Ergebnis 1       
    unsigned short Ext_Sensor2;     //Ergebnis 2      
    unsigned short Ext_Sensor3;     //Ergebnis 3       
    unsigned short Ext_Sensor4;     //Ergebnis 4
    unsigned short Ext_Sensor5;     //Ergebnis 5
    unsigned short Ext_Sensor6;     //Ergebnis 6
    unsigned short Ext_Sensor7;     //Ergebnis 7
    unsigned short Ext_Sensor8;     //Ergebnis 8
    unsigned short reserved1;   //Ergebnis 9
    unsigned short reserved2;   //Ergebnis 10
    unsigned short reserved3;   //Ergebnis 11
    unsigned short reserved4;   //Ergebnis 12
    unsigned short reserved5;   //Ergebnis 13
    unsigned short reserved6;   //Ergebnis 14
    unsigned short reserved7;   //Ergebnis 15
    unsigned short reserved8;   //Ergebnis 16

} __attribute__ ((packed));

#endif /* ADC_H_ */

Adc.c

/*
 * ADC.c
 *
 *  Created on: 03.04.2012
 *      Author:
 */

#include "Adc.h"

struct Adc1_Result *ADC1 = ADRESSE_ADC1;

Greetings, Andi

Andi,

Are you using the 470 compiler or another? I cannot get the TI compiler to accept the

struct Adc1_Result *ADC1 = ADRESSE_ADC1;

It gives the warning "a value of "int" cannot be used to initialize an entity of type "struct Adc1_Result"

Thanks,

Pat

Pat,

please add in Adc.h:

#define ADRESSE_ADC1 (struct Adc1_Result *) 0x50001600  //Startadresse ADC1-Result-Register M3
#define ADRESSE_ADC2 (struct Adc2_Result *) 0x50001680  //Startadresse ADC2-Result-Register M3

The warning will disappear. Thanks for recognizing me to fix this warning.

Andi

Thanks Andi. That eliminated the warning.

My problem lies on the C28 side, apparently. I am trying to modify the PLC example application that uses DSP/BIOS. It is not clear to me what modifications I should make. I have created a seperate task for the analog service and would like to just service the ADC during this task rather than using the interrupt service method used in the adc examples for the C28. Will this work or what would reccommend? Could you show the setup procedure required for this method?

Thanks,

Pat

Here is my initialization sequence. This is mostly like that for adc_soc example:

The initAdc1() routine (below), followed by the PIE init. code :

PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

IER |= M_INT1;

Followed by the configuration code, ConfigAdc1() (below, following InitAdc): Could you take a look at this code to see if I have / where I have made mistakes?

InitAdc();

// Enable CPU Interrupt 1

//---------------------------------------------------------------------------

// InitAdc1:

//---------------------------------------------------------------------------

// This function initializes ADC1 to a known state.

void

InitAdc1(void)

{

extern void DSP28x_usDelay(Uint32 Count);

// To powerup the ADC1 the ADC1ENCLK bit should be set first to enable

// clocks, followed by powering up the bandgap, reference circuitry, and

// ADC1 core.

// Before the first conversion is performed a 5ms delay must be observed

// after power up to give all analog circuits time to power up and settle

// Please note that for the delay function below to operate correctly the

// CPU_RATE define statement in the F28M35xA_Examples.h file must

// contain the correct CPU clock period in nanoseconds.

EALLOW;

Adc1Regs.ADCCTL1.bit.RESET = 1;

// added reset prh 7/14/12

asm(" NOP ");

asm(" NOP ");

Adc1Regs.ADCCTL1.bit.ADCBGPWD = 1;

// Power ADC1 BG

DELAY_US(ADC_usDELAY);

// Delay before converting ADC1 channels

// Adc1Regs.ADCCTL1.bit.ADCREFSEL = 0; // Select interal BG

Adc1Regs.ADCCTL1.bit.ADCREFSEL = 1;

// Select interal BG

Adc1Regs.ADCCTL1.bit.ADCREFPWD = 1;

// Power reference

Adc1Regs.ADCCTL1.bit.ADCPWDN = 1;

// Power ADC1

DELAY_US(ADC_usDELAY);

// Delay before converting ADC1 channels

Adc1Regs.ADCCTL1.bit.ADCENABLE = 1;

// Enable ADC1

EDIS;

DELAY_US(ADC_usDELAY);

}

ConfigAdc1();

void

ConfigAdc1( void)

{

// Configure ADC

EALLOW;

Adc1Regs.ADCCTL2.bit.ADCNONOVERLAP = 1;

// Set ADC to non-overlap mode

Adc1Regs.ADCCTL1.bit.INTPULSEPOS = 1;

// EOC trips after conversion result is latched

Adc1Regs.INTSEL1N2.bit.INT1E = 1;

// Enabled ADCINT1

Adc1Regs.INTSEL1N2.bit.INT1CONT = 0;

// Disable ADCINT1 Continuous mode

Adc1Regs.INTSEL1N2.bit.INT1SEL = 1;

// setup EOC1 to trigger ADCINT1

// Select ADC input channels

Adc1Regs.ADCSOC0CTL.bit.CHSEL = 0;

// set SOC0 channel select to ADC1A0

Adc1Regs.ADCSOC1CTL.bit.CHSEL = 2;

// set SOC1 channel select to ADC1A2

Adc1Regs.ADCSOC2CTL.bit.CHSEL = 3;

// set SOC2 channel select to ADC1A3

Adc1Regs.ADCSOC3CTL.bit.CHSEL = 4;

// set SOC3 channel select to ADC1A4

Adc1Regs.ADCSOC4CTL.bit.CHSEL = 6;

// set SOC4 channel select to ADC1A6

Adc1Regs.ADCSOC5CTL.bit.CHSEL = 7;

// set SOC5 channel select to ADC1A7

Adc1Regs.ADCSOC6CTL.bit.CHSEL = 12;

// set SOC6 channel select to ADC1B4

Adc1Regs.ADCSOC7CTL.bit.CHSEL = 13;

// set SOC7 to Vref

// Setup ADCINT1 and ADCINT2 trigger source

Adc1Regs.INTSEL1N2.bit.INT1SEL = 6;

//EOC6 triggers ADCINT1

Adc1Regs.INTSEL1N2.bit.INT2SEL = 14;

//EOC14 triggers ADCINT2

// Setup each SOC's ADCINT trigger source

Adc1Regs.ADCINTSOCSEL1.bit.SOC0 = 2;

//ADCINT2 starts SOC0-7

Adc1Regs.ADCINTSOCSEL1.bit.SOC1 = 2;

Adc1Regs.ADCINTSOCSEL1.bit.SOC2 = 2;

Adc1Regs.ADCINTSOCSEL1.bit.SOC3 = 2;

Adc1Regs.ADCINTSOCSEL1.bit.SOC4 = 2;

Adc1Regs.ADCINTSOCSEL1.bit.SOC5 = 2;

Adc1Regs.ADCINTSOCSEL1.bit.SOC6 = 2;

// Selecing triggers for SOCs

// AnalogSysctrlRegs.TRIG5SEL.all = 5; // Assigning EPWM1SOCA to TRIGGER 5 of analog subsystem

// AnalogSysctrlRegs.TRIG6SEL.all = 6; // Assigning EPWM1SOCB to TRIGGER 6 of analog subsystem

// Adc1Regs.ADCSOC0CTL.bit.TRIGSEL = 9; // Assign EPWM1SOCA to SOC0 TRIGSEL

// Adc1Regs.ADCSOC1CTL.bit.TRIGSEL = 10; // Assign EPWM1SOCB to SOC1 TRIGSEL

// Set S/H window of 7 ADC clock cycles

Adc1Regs.ADCSOC0CTL.bit.ACQPS = 6;

// S/H = ACQPS + 1

Adc1Regs.ADCSOC1CTL.bit.ACQPS = 6;

Adc1Regs.ADCSOC2CTL.bit.ACQPS = 6;

Adc1Regs.ADCSOC3CTL.bit.ACQPS = 6;

Adc1Regs.ADCSOC4CTL.bit.ACQPS = 6;

Adc1Regs.ADCSOC5CTL.bit.ACQPS = 6;

Adc1Regs.ADCSOC6CTL.bit.ACQPS = 6;

EDIS;

}