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F28335 IER and PIEIER registers

Ganga Jayaraman
Prodigy 160 points

Hi,

I have a kind of basic question to which I couldn't find a satisfactory answer in the user guides. When a peripheral interrupt is acknowledged by the CPU I understand that the corresponding IER bit is cleared as soon as the ISR begins to execute. When is it set again? Is it done by the user inside the ISR or is it done by the CPU or PIE automatically upon the completion of the ISR?

Similarly, at the time of the occurrence of the peripheral interrupt I understand that the PIEIER bit is set. Is it ever cleared by the PIE or the CPU? If so, how is it set again?

I understand how the IFR and PIEIFR register bits work in that they are automatically set and cleared by the hardware and the user should never have to worry about that.

Thanks,

Ganga

 

  • 0
    TI__Genius 15260 points

    Hi Ganga,

    Have you had a chance to look through the System Control & Interrupts Guide for your device?  It can be found here:

    http://www.ti.com/lit/ug/sprufb0d/sprufb0d.pdf

    I believe you are confusing IER and IFR in your references above.  The IER register is the "Interrupt Enable Register" and will always be modified strictly by the user to enable or disable interrupts from reaching the CPU.

    I believe if you use the above link and reference pg 122 this will answer all of your questions as it covers this topic in detail.  Please let me know if you still have questions afterwards. 

    Kris

  • 0 in reply to Kris Parrent
    Prodigy 160 points

    Krris,

    Thanks for replying to my query. I figured out that the IER register flag is cleared by the CPU before it enters the ISR, and then the flag is enabled again when the CPU context is restored by the hardware when it returns from the ISR. The user has the option to enable it when entering the ISR to permit nested interrupts. As you pointed out the IFR is managed entirely by the hardware.

    For the PIE interrupt, the PIEIER register flag is enabled once by the user at startup, it is not subsequently changed. The corresponding PIEACK flag is cleared by the hardware when the interrupt is accepted byt eh CPU. The user enables the PIEACKx flag after entering the ISR so that further interrupts from theat PIE module can be recieved. The PIEIFR register is again managed by the hardware.

    Thanks,

    Ganga

  • 0 in reply to Ganga Jayaraman
    Prodigy 160 points

    Correction:

    For the PIE interrupt, the PIEIER register flag is enabled once by the user at startup, it is not subsequently changed. The corresponding PIEACK flag is set by the hardware when the interrupt is accepted by the CPU. The user clears the PIEACKx flag by writing a 1 after entering the ISR so that further interrupts from theat PIE module can be recieved. The PIEIFR register is again managed by the hardware.