Best C2000 A/D for deterministic sampling

Steveg,

I am not sure about your MSPS requirements and other peripherals/frequency  requirements, i recommend you go through the

Table 2-1. F2833x Hardware Features in the Literature Number: SPRS439J.  All these devices F28335 (150 MHz), F28334 (150 MHz), F28332 (100 MHz) has TYPE 2 12it ADC, below are the snapshot features which will meet your requirement for sampling the signals in the same order with exactly the same amount of time between samples

12-Bit ADC, 16 Channels

• 80-ns Conversion Rate
  2 x 8 Channel Input Multiplexer
  Two Sample-and-Hold
  Single/Simultaneous Conversions
  Internal or External Reference

Regards,

Mahesh

Thanks, so the SOC type of A/D's in the Concerto parts wouldn't be appropriate for what I need? They seem to have a random jitter due to the clock differences between the CPU and A/D.

Hi Steveg

With how much jitter can you get by? I really recommend that you read the electrical specification regarding AD for each part. If SOC trigger comes from internal peripheral and with proper setup there can be no jitter (with reference to CPU clock). Keep in mind that you can only sample 2 channels at the same time and that you don't have direct control over sampling instant (by that I mean the instant when S/H phase of conversion ends), so you always have to do a bit of math to properly configure SOC trigger

Regards, Mitja

As I mentioned in my original post, 1 clock.

I read the electrical specifications for the A/D, they aren't helpful since they only specifiy the ADC specs as an isolated part.

I am interested in the A/D system specifications.

If you refer to the Concerto training slides on the A/D subsystem, page 10

http://focus.ti.com/download/mcu/TI_Concerto_College_Topic_05_AnaloglSubSystem(1).pdf

they talk about jitter of the A/D, basically 9 to 14 clock cycles from the start of SOC to the sample and hold, this is unacceptable for my application.

I can deal with a fixed known latency, I can't deal with random latency (i.e., jitter).

In the Concerto College slide package they say the jitter is due to the fact the PLL clock and A/D clock are running at different rates, and they say this occcurs on other C2000 parts, but don't specific which parts.

Steve,

Concerto will not be the series of parts for you due to the issues you mention.  There is some unknown (but bounded) latency with regard to this part.

The other C2000 families such as the, Piccolo F2802x, Piccolo F2803x, Piccolo F2806x, Delfino F2833x, etc will have more manageable latencies.  The ADC sample point and amount of time to get from ADC-to-register will be fixed.

I'd suggest researching in this direction.


Thank you,
Brett

Brett,

Ok, thanks!

Steve

Brett,

while we're at it I was thinking of writing a test case with ePWM acting as a trigger to ADC. My idea was to monitor fixed frequency, fixed duty cycle PWM signal and ADCSOCAO signal and measuring the jitter between them. But going through the documentation it is not clear how is the ADCSOCAO generated. If it is by ePWM than you don't get any information by measuring the jitter between these two. It would be nice if documentation (electrical specs) included a timing diagram how ADSOCAO is related to other ADC signals.

Steve,

For some older 280x parts (e.g. 2808) there was a fixed delay (2.5 ADCCLK cycles if I remember correctly) between receiving SOC signal and opening S/H line. Obviously this could cause a problem if SOC signal generation was done off a different clock source as you already mentioned. A possible workaround would be to configure ePWM to have the same clock speed ad ADC and use it as a SOC signal source. I don't know if this would work in your application.

Regards, Mitja