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F28335 SCI TXEMPTY bit



Hi all,

I'm using a F28335 and I'm having some troubles with the SCI in FIFO mode at 38400 bauds.

I need to disconnect the transmiter after sending the last bit of the last byte. According to the datasheet, I check for TXEMPTY = 1 (in SCICTL2 reg). But it goes to 1 around 1 byte before the last bit of the last byte goes out.

Is the TXEMPTY bit working well in FIFO mode?

In FIFO mode, does it go to 1 when the SCITXBUF and TXSHF are both empty?

Does the TXEMPTY have in account the STOP bit?

I see some questions in the forums, but none of them clarified me this issue.

Thank you for the answers.

Josep

  • Josep,

    I checked the SCI user guide (SPRUFZ5A) and I did not see any reason for this behavior.  TX EMPTY is described as 1 when both the SCITXBUF and TXSHF registers are empty.  I also did not see any comments indicating that FIFO mode would affect this behavior.

    I do not think TX EMPTY takes in to account the STOP bit(s) as those bits are unrelated to the physical registers checked.

    Regards,
    Daniel

  • Daniel,

    Thanks for your answer.

    This is what I thought reading de UG SPRUFZ5A but there are some things that not remain clear for me.

    It seemed to me that the stop bit was not taken in to account in TX EMPTY signal/bit but graph of page 21 of the UG seems to say the opposite.

    The code bellow and the graph of the oscilloscope shows what I've got.

    This portion of code runs inside a loop and is executed every 2 uS

    Ch2 is the TX pin of the F28335. This is the complete frame of 9 bytes (Start, 8bits, no parity, 1 Stop) preloaded all of them together.

    Ch3 is an output pin of the cpu, set and reset by "SET_TEST_C and RESET_TEST_C" the width of the pulse corresponds to the width of 1 byte (first byte) without the stop bit.

     

    if (SciaRegs.SCICTL2.bit.TXEMPTY == 1) SET_TEST_C

    else RESET_TEST_C

    if (SciaRegs.SCICTL2.bit.TXEMPTY == 1 && SciaRegs.SCIFFTX.bit.TXFFST == 0 && iEndTx==TRUE) {

         iEndTx = FALSE;

         iTimerEndTx = iTimerEndTxReload;

         }

    if (iTimerEndTx == 0) {

         SCI_485TXOFF();

        iTimerEndTx = -1;

        }

     Osciloscope image

     

     

     

     

     

     

     

     


     

     

     

    What do you think?

     

    Regards,

    Josep

     

     

  • Josep,

    I would treat the diagram as more of a "reference example" than an "exact example"

    Have you tried stepping through the code and looking at the register bit directly?

    Regards,
    Daniel

  • Also, what are SET_TEST_C and RESET_TEST_C

  • Daniel,

    yes, I stepped trougth the code and the TX EMPTY bit allways goes to 1 when the first byte is out as I can see on the oscilloscope.

    SET_TEST_C and RESET_TEST_C are two macros that set and reset a GPIO bit of the CPU and corresponds to the Ch3 in the graph of the oscilloscope. In the code and graphs above, this shows how the TX EMPTY bit changes with a accuracy of about 2uS.

    At the moment the only way to do this code working is, checking the field TXFFST of the SCIFFTX register for 0 (0 bytes in the buffer) and then start a timer with a value according to the baudrate plus a margin and when the timer expires, switch off the transmitter.

    This works well, but what I'd to know, if this is an issue of the SCI or I'm doing something wrong. I've seen other posts in the forums talking about similar problems with no clear answers and with no much intervention of TI employees ????

    Regards,

    Josep

  • Josep,

    I have asked our SCI expert to comment on this issue. 

    Regards,
    Daniel

  • Josep,

    Are you using GPIO set and clear registers to set/clear the GPIO OR Are you using GPIO toggle register in your set and reset functions?

    Thanks and regards,
    Vamsi

  • Hi Vamsi,

    I'm using set and clear registers.

    Regards,

    Josep

     

  • Josep,

    Thank you for the clarification.

    You mentioned that "But it goes to 1 around 1 byte before the last bit of the last byte goes out."  Could you explain your observation clearly?

    Do you mean that TXEMPTY is getting set even when there are more bytes in TX FIFO that have to be transmitted?  If yes, what is the pattern that you observed?  Did you observe that TXEMPTY is getting set after every byte is sent out from TXSHF in FIFO mode and getting cleared when again TXSHF starts transmitting next byte in FIFO? or Did you observe that TXEMPTY gets set after sending the first one byte from FIFO and it remains set until all the bytes in FIFO are sent out from TXSHF?

    Thanks and regards,

    Vamsi

     

  • Vamsi,

    Thaks for your time.

    I checked what I've wrote above and in fact it do not remains clear because between my first post and the other posts, I've done more tests.

    What I do and what I get:

    1.- I load the TX buffer (SCITXBUF) with 9 bytes.

    2.- After that, the program falls in a loop wherever max. 2 uS the following code is executed.

    if (SciaRegs.SCICTL2.bit.TXEMPTY == 1) SET_TEST_C

    else RESET_TEST_C

    if (SciaRegs.SCICTL2.bit.TXEMPTY == 1 && SciaRegs.SCIFFTX.bit.TXFFST == 0 && iEndTx==TRUE) {

         iEndTx = FALSE;

         iTimerEndTx = iTimerEndTxReload;

         }

    if (iTimerEndTx == 0) {

         SCI_485TXOFF();

        iTimerEndTx = -1;

        }

    3.- The signals that I see on the oscilloscope (graph above) are that, the TEST signal (GPIO out), that is a copy of TX EMPTY bit with an accuracy of 2 uS, is set after the first byte is sent out from the TXSHF register and remains set until I reload a new frame (9 bytes) and then is cleared for the first byte again.

    Hope this clarifies a bit more.

    Thanks and regards,

    Josep

     

     

     

  • Josep,

    Let me try some experiments and will get back to you next week.

    Thanks and regards,
    Vamsi