SCI Rx FIFO ISR

Other Parts Discussed in Thread: CONTROLSUITE

Hi Folks

Im struggling a bit setting up the SCIa with FIFO and interrupts. I have a program using the SCI FIFO that uses polling instead of interrupts working, no problem.

However I am attempting to use interrupts now instead and two things are happening that I dont understand: 1) the Tx interrupt fires once as soon as the interrupts are enabled 2) The Rx interrupt never runs (never gets to a break point at the first instruction inside of it)

I am using a very similar setup to the sci feedback loop with interrupts example program except with loop back not enabled, but just cannot understand why the above.

below is my sciaFIFOinit function and my Rx and Tx ints the Tx does nothing for now, I just want to try and read some data in to begin with.

The init function is called from the main() just after the deviceInit and flash init section and the EINT; is the next instruction after that the program is sitting in a while loop doing nothing. The data is sent on the USB by a vb program that has been tested to work with the non-interrupt version of the program.

void sciaFifoInit(void) {
	EALLOW;								// Map SCI interrupts to ISR functions
	PieVectTable.SCIRXINTA = &sciaRxFifoIsr;
	PieVectTable.SCITXINTA = &sciaTxFifoIsr;
	EDIS;
	SciaRegs.SCICCR.all =0x0007;		// 1 Stop bit,  no loopback
										// no parity, 8 char bits,
										// async mode, idle-line protocol
	SciaRegs.SCICTL1.all =0x0003;		// Enable TX, RX, internal SCICLK,
										// disable RX ERR, SLEEP, TXWAKE
	SciaRegs.SCICTL2.bit.TXINTENA =1;	// Enable Tx interrupt
	SciaRegs.SCICTL2.bit.RXBKINTENA =1;	// Enable RX interrupt
	SciaRegs.SCIHBAUD = 0x0000;  		// SCI BRR = LSPCLK/(SCI BAUDx8) - 1
	SciaRegs.SCILBAUD = 0x00C2;			// BRR = (15MHz/(Baud x 8)) - 1. 9600 Baud = 194d = C2h.
	SciaRegs.SCIFFTX.all = 0xC022;		// Hold SCI in reset, enable FIFO, hold FIFO in reset, clear FIFO status, clear int, enable int,  set int level to 0 
	SciaRegs.SCIFFRX.all = 0x0022;		// Clear overflow flag, hold FIFO in reset, clear FIFO status, clear int, enable int, set int level to 3 
	SciaRegs.SCIFFCT.all = 0x00;		// Disable auto-baud feature and set Tx delay to 0
	
	SciaRegs.SCICTL1.all = 0x0023;     // Relinquish SCI from Reset
	SciaRegs.SCIFFTX.bit.TXFIFOXRESET = 1;
	SciaRegs.SCIFFRX.bit.RXFIFORESET = 1;
	PieCtrlRegs.PIECTRL.bit.ENPIE = 1;	// Enable the PIE block
	PieCtrlRegs.PIEIER9.bit.INTx1=1;	// PIE Group 9, INT1
	PieCtrlRegs.PIEIER9.bit.INTx2=1;	// PIE Group 9, INT2
	IER |= M_INT9;
}

interrupt void sciaRxFifoIsr (void) {
	// SCI FIFO interrupt (SCIRXINTA) indicating the SCI FIFO has recieved some data
	Uint16 rxBuffer[CNTRL_BUF_LEN];
    Uint16 i;
	for (i=0; i<CNTRL_BUF_LEN; i++)	{
		rxBuffer[i] = SciaRegs.SCIRXBUF.all;		// Read into buffer byte-by-byte 
	}
	
	sciaTx(0);									// Tx response to confirm reciept
	SciaRegs.SCIFFRX.bit.RXFFOVRCLR=1;		// Clear Overflow flag
	SciaRegs.SCIFFRX.bit.RXFFINTCLR=1;		// Clear Interrupt flag
	PieCtrlRegs.PIEACK.bit.ACK9 = 1;				// Acknowledge CPU interrupt
}

interrupt void sciaTxFifoIsr(void) {
    PieCtrlRegs.PIEACK.bit.ACK9 = 1;							// Acknowledge CPU interrupt
}