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Implementation of control loop on f28069?

Peter C
Prodigy 200 points

Hello everyone

I am currently trying to implement a control loop on a F28069. It is peak current mode control of a smps. 

Basically, i am running the epwm with a specific frequency. I have then hooked up the comparator to pull the epwm low, whenever the current ramp from the current sense resistor is higher than the output of the DAC. The DAC is controlled by a compensator(PI), which is based on the output voltage of the converter. The pwm sends a SOC interrupt to the ADC whnever it is pulled down, in order to start the ADC sampling, and the ADC will also send an interrupt when it is done sampling(EOC).

The main question is about implementing the control loop. I am using the IQmath to do the calculations, and i need to do 5 multiplications. I am running the five multiplications in the main loop, and whenever the ADC SOC interrupts come on, move all samples one down the line(e[n] becomes e[n-1] and so on]. 

However, i feel that this solution is a bit strange and not optimal, in fact i cant get it working. I fear that the MCU is too slow to run those 5 multiplications before the interrupt comes on. How would i go about optimizing it, so i have the time for the control loop and other tasks? For instance, there is no sense in running the comparator calculations all the time. It should only be necessary to run it once, whenever the interrupt has been triggered. But placing the heavy multiplication code in the interrupt seems like a bad idea. 

And how about the multiplication? I understand that IQmath is pretty fast, but i am stil concerned about the speed. Would there be a better way to implement the multiplications? I could ofcause implement the control loop in the CLA, but i would like to keep away from assembly if at all possible. 

What are your thoughts on this? I have read an application note(SPRABE7), but there is really no actual example code.

What are your suggestions and ideas for making this run smooth?

Best regards Peter

  • TI__Genius 10820 points

     Hello Peter,

    When you say you are running the 5 multiplications in the main loop, do you mean you are executing the control loop from the background code and not a PWM/ADC triggered interrupt? What PWM frequencies are you switching at and what control frequency do you desire?

    Typically in such an appllication the time critical code involves reading of the ADC result, execution of the control code (PI/PID/2P2Z), and update of the control action (writing to the DAC in your case). This time critical part of code typically resides in the ISR triggered by the PWM or ADC at or at integral multiples of PWM switching frequency. This allows the newly calculated control action to take effect at known good points within a PWM cycle (for example, at the start of a new cycle). Other system level tasks that are not necessary to be executed at the control loop rate are located in the background loop.

    For high frequencies every cycle counts. In these cases writing your code in assembly is helpful. To ease programming burden in high frequency applications (>50/100 KHz), TI provides a digital power library that includes optimized assembly macros for standard functions, control loops and power topologies. CLA version of this library also exists.

    A number of applications and systems have successfully been implemented with these MCUs for control loops running at 100s of KHz. I will be very surprised if you find that the MCU is not fast enough for your application after implementing above software structure.

    There are a number of digital power application kits that you might find helpful. The software and documentation are free to download. You may start looking through the 2-channel DC-DC kit first to understand the software architecture and library usage. A peak current mode control system is implemented in the HVPSFB kit. All these kits, software and documentations can be found at http://ti.com/c2000tools 

    Since you are implementing peak current mode control, you might also be interested in the built in hardware slope compensation mechanism available on Piccolo devices. You can find more information in spruge5f.

    I hope this helps.

    Hrishi

  • in reply to Hrishi Nene
    Prodigy 200 points

    Hi Hrishi,

    Thank you very much for your answer. It is always nice to know if i am doing things right.

    I am running the PWM module at 100kHz. I then trigger the output low using the comparator. At the same time, an interrupt starts the ADC conversion. When the ADC is done, an interrupt is sent to the CPU. This interrupt then runs the code in order to update the control values to the newest values:

    n[-2] = n[-1];

    n[-1] = n[0];

    e[-2] = e[-1];

    e[-1] = e[n];

    run_compensator = 1;

    In the main loop, there is a function called compensator(), which is run once, whenever run_compensator is 1. This is working fine. Previously, i was just running the compensator function for every iteration of the forever loop, and this caused some problems getting everything running, for some reason. The comparator() function basically only contains 6 multiplications (IQrsmpy(x,y)) and a write to the DAC value register. As i see it, the interrupt from an ADC should trigger an interrupt, and allowing 30 cycles for each multiplication gives me a total time of 2.25us, well below the 10us interrupt period from the ADC. The duty is limited to 50%(by use of CPMA), leaving 5us for ADC sampling, interrupt and multiplication. The ADC sample is 64 clocks, and including the conversion time of 13 cycles, this adds up to 0.96us. Thus, from the trigger point(when pwm goes low), there is a total of (2.25+0.96)us to calculate the compensator loop and writing new values to the DAC register. Even though i am ignoring the interrupt delay time, i would expect the MCU to be able to handle everything needed within those 5us. And it runes fine, when i only run the comparator() function once every pwm cycle. But when i keep it free running, i get some sort of error. 

    The main question now, is more a control-related issue. I am experiencing what i believe to be limit cycling. Even though the error e[n] is only off by at most 1 lsb(when observed from the watch window), the value written to the comparator DAC is fluctuating by around 35-40 LSBs. I tried reducing the effective number of bits of the ADC in order to ensure that there is no more than 1 error level that maps into each DAC output LSB. This was done by just right-shifting the ADC by 4, effectively converting it into an 8 bit ADC. However, this did not provide any improvement on the limit cycling. This leads me to belive that i am having problems with the integrator gain in my system. If the integrator gain is too high, the compensator is unable to stabilize itself within one DAC lsb bin, but will keep fluctuating around several bins. And i am a bit puzzled by how i can reduce the integral gain of my PI controller without a severe bandwidth punishment. 

    But the software part of the converter now functions without any problems(apart from the limit cycling). But i will look into the sources you mentioned and see if they address the limit cycling issue. In any case i would like to thank you for answering. 

    Br Peter