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Problem with GPIO register setup

Other Parts Discussed in Thread: TMS320F2812

Hello,

An odd issue comes up in the code that is written for TMS320F2812 and attached below. The program just outputs a square wave that is generated with timer 1 in event manager A. Before setting up the required registers for this task, I configure all GPIO pins as digital outputs and set them to 0 to not have the floating pins as inputs (as recommended in the hardware design guidelines).

The problem is now that the code does not work if bit 0 of GPIO D (T1CTRIP_PDPINTA) is cleared. Please see the highlighted line in the code below. If FFFF is written into the clear register of GPIO D (like in all the others), the square wave is not output any more. Instead the signal is constantly high. If the LSB of GPIO D is not cleared on the other hand, by writing FFFE, then it works fine. I am aware that the trip function can set the compare output to high Z but still find the behaviour surprising because GPDMUX is set to 0 before and indeed is 0 at runtime, telling the pin to have the digital I/O function and not the peripheral functionality, and moreover the bit is supposed to be 0 after reset anyway.

What could be the reason?

Regards,

Adrian

/*
 * timertry_T1PWM
 * main.c
 *
 * use the GP timer compare unit of event manager A, timer 1, to get a PWM signal with f = 20 kHz
 * GP timer 1 uses its own compare functionality (output T1PWM)
 * output pin: T1PWM (pin 15)
 *
 */
#include "DSP281x_Device.h"
#include "math.h"
extern void InitSysCtrl(void);

void main() {
    float d=0.77;
    InitSysCtrl();

// configure all GPIO pins as digital outputs and set to 0
    EALLOW;
    GpioMuxRegs.GPAMUX.all=0;
    GpioMuxRegs.GPBMUX.all=0;
    GpioMuxRegs.GPDMUX.all=0;
    GpioMuxRegs.GPEMUX.all=0;
    GpioMuxRegs.GPFMUX.all=0;
    GpioMuxRegs.GPGMUX.all=0;
    GpioMuxRegs.GPADIR.all=0xFFFF;
    GpioMuxRegs.GPBDIR.all=0xFFFF;
    GpioMuxRegs.GPDDIR.all=0xFFFF;
    GpioMuxRegs.GPEDIR.all=0xFFFF;
    GpioMuxRegs.GPFDIR.all=0xFFFF;
    GpioMuxRegs.GPGDIR.all=0xFFFF;
    GpioDataRegs.GPACLEAR.all=0xFFFF;
    GpioDataRegs.GPBCLEAR.all=0xFFFF;
    GpioDataRegs.GPDCLEAR.all=0xFFFE;    // oddity here
                 If FFFF is written into the clear register, the program does not work any more.
    GpioDataRegs.GPECLEAR.all=0xFFFF;
    GpioDataRegs.GPFCLEAR.all=0xFFFF;
    GpioDataRegs.GPGCLEAR.all=0xFFFF;
    EDIS;

// configure required GPIO pins as peripheral (here: timer) outputs (digital I/O)
    EALLOW;
    GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6=1;
    EDIS;

// GP timer 1 setup
    EvaRegs.T1CON.bit.FREE=0;        // stop immediately on emulation suspend
    EvaRegs.T1CON.bit.SOFT=0;        // ... second part of it
    EvaRegs.T1CON.bit.TMODE=2;        // continuous up-counting mode
    EvaRegs.T1CON.bit.TPS=0;        // input clock prescaler, corresponds to factor 1
    EvaRegs.T1CON.bit.TENABLE=1;    // enable timer
    EvaRegs.T1CON.bit.TCLKS10=0;    // use HSPCLK as clock
    EvaRegs.T1CON.bit.TCLD10=0;        // reload compare register T1CMPR at beginning of switching period
    EvaRegs.T1CON.bit.TECMPR=1;        // enable timer compare

    EvaRegs.T1PR=7499;                // period register = 150MHz/20kHz-1 (HISPCP = 1, TPS = 0)
    EvaRegs.T1CMPR=floor(EvaRegs.T1PR*d);    // compare register for T1PWM
    EvaRegs.T1CNT=0;                // initialize counter register

// GP timer control register of EVA (for T1PWM)
    EvaRegs.GPTCONA.bit.T1CTRIPE=0;    // disable trip function that can drive output to high Z
    EvaRegs.GPTCONA.bit.TCMPOE=1;    // enable compare output
    EvaRegs.GPTCONA.bit.T1TOADC=0;    // don't set off ADC
    EvaRegs.GPTCONA.bit.TCMPOE=1;    // enable timer compare outputs
    EvaRegs.GPTCONA.bit.T1CMPOE=1;    // enable timer 1 compare outputs
    EvaRegs.GPTCONA.bit.T1PIN=1;    // polarity of T1PWM (1 = active L, 2 = active H)

    while(1){
    ;
    }
}

  • Adrian,

    Can you verify in the Watch Window that the GPIOD0 mux bit is actually set to 0?  

    Can you also check if the T1CTRIP_PDPINTA is enabled in the event manager?  Have you checked the T1CTRIP flags afterwards to see if they are set indicating a trip?

    Kris

  • Hello Kris,

    Kris Parrent said:
    Can you verify in the Watch Window that the GPIOD0 mux bit is actually set to 0?


    Yes, so it displays.

    Kris Parrent said:
    Can you also check if the T1CTRIP_PDPINTA is enabled in the event manager?


    The code contains the line
    EvaRegs.GPTCONA.bit.T1CTRIPE=0;
    which should disable the trip function. The bit is indeed zero.

    Kris Parrent said:
    Have you checked the T1CTRIP flags afterwards to see if they are set indicating a trip?


    The Power Drive Protection Interrupt Flag EVAIFRA[0]=1 -- I hope this is what you mean. I have tried resetting it initially via
    EvaRegs.EVAIFRA.bit.PDPINTA=1;
    Then it is 0 after suspending the emulation, but the output still does not work. Apparently the bit is already set when the device is started unless one resets it explicitly. But either way the behaviour is the same.

  • Can you try moving the EvaRegs.GPTCONA.bit.T1CTRIPE=0; prior to clearing the pin?  

    Can you verify the PDPINTA flag is NOT set before clearing the GPIO (on first run after device power up)?  

    Kris

  • Kris Parrent said:
    Can you try moving the EvaRegs.GPTCONA.bit.T1CTRIPE=0; prior to clearing the pin?

    Moving the line just below InitSysCtrl() and above the GPIO register manipulations does not make a difference regarding the output.

    Kris Parrent said:
    Can you verify the PDPINTA flag is NOT set before clearing the GPIO (on first run after device power up)?

    Before the main routine is executed, EVAIFRA=0. EVAIFRA[0] remains 0 when the instruction says GpioDataRegs.GPDCLEAR.all=0xFFFE; and changes to 1 when the code line is GpioDataRegs.GPDCLEAR.all=0xFFFF;

  • I apologize for the delay in getting back to you.  Have you managed to resolve this issue?

    Kris

  • No, it still is the same. I use the posted code and the program runs like this. Setting the pin as an output when it is floating is, as I understand it, a good idea to prevent dirt effects that can occur because of noise. But since I do not use the functionality of the pin, this oddity is not my main concern now.

  • Thank you for the confirmation.  I'm working on getting a hold of a board so I can look into this issue.  As soon as I have an update I will get back to you.  If this is not high priority for you, would sometime in the next 1-2 weeks be fine?  Thanks,

    Kris

  • Hello Kris, thanks for looking into this further. Sometime in the next few weeks is totally fine.

  • Looks like this is expected behavior.  By default, the PDPINTx is enabled on reset since it is a protection feature.  Even though your mux is configured to GPIO, this is still monitoring the status of the pin in order to hi-z the output.  So when you're clearing the GPIO, the PDPINT is seeing the GPIO low signal and is setting the flag.  What you need to do is mask this before you set the GPIO low.

    To do this, clear the PDPINTA bit in the EVAIMRA register prior to clearing your GPIO.  I believe this will solve your problem with the PWM outputs being disabled when you configure them.

    Kris