Some GPIO not working on Concerto

Pat,

to write '1' to an IO, for ex GPIO_PIN_3 of GPIO_PORT_G, you need to do below.

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,GPIO_PIN_3);

to write a '0' to the same IO, you need to do below

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,~GPIO_PIN_3);

can you correct your code and see if that fixes the error.

 

Best Regards

Santosh

Santosh,

Thanks for your reply, That change did not make any difference. My concern is that, for some reason, the CM3 side will not program the GPIO reliably, I believe the intent was for the C28 side to do all the peripheral IO. Do you recommend switching to the C28 side? Is there a problem with the specification in this regard? I just found out that the ACIB will not work on the CM3 side as the spec indicates and that the spec. needs to be corrected. Is this another correction?

Thanks,

Pat

 

Pat,

All IO by default are controlled by master subsystem. Both Master and Control subsystems should be able to toggle IOs as per the ownership config. There are no problems with the specification in this regard. Can you clarify if you are not seeing PG0, PG1 and PG3 go HIGH/LOW, alos can you clarify if you are doing peripheral enable and peripheral reset before writing to the GPIO BASE registers?

Pat Harris said:

I just found out that the ACIB will not work on the CM3 side as the spec indicates and that the spec. needs to be corrected. Is this another correction?

Can you please clarify above, what is not working on ACIB on M3 side? it would help if you can point out what needs to be corrected in the spec and how you concluded this? is there another forum post on this or errata that you are referring to?

 

Best Regards

Santosh

Santosh,

Here is the other post.

http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/p/138792/698871.aspx#698871

Pat

 

Santosh,

I first call my configuration file:

 

Config_c28x(void) {   // Disable Protection   HWREG(SYSCTL_MWRALLOW) =  0xA5A5A5A5;

  // Setup main clock tree for 75MHz - M3 and 150MHz - C28x   SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |                        (SYSCTL_SPLLIMULT_M & 0x0F));   // enable serial uart port 0   SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);      // Enable all GPIOs   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);   SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

  // a "1" gives C28 control of GPIO bits, "0" gives CM3 control   // PC6&7 - LED2 and LED3 on Concerto card, PH3 & PF2 - LD4&5 on docking station,   // and PB0, PA6&7 (AFED1,2,3 on AFE board) are config to CM3    //  GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0x3F, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTB_BASE, 0xFE, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, 0x3F, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTD_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0xCF, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0xFB, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_C_CORE_SELECT); //  GPIOPinConfigureCoreSelect(GPIO_PORTH_BASE, 0xF7, GPIO_PIN_C_CORE_SELECT);

    // a "1" gives C28 control of GPIO bits, "0" gives CM3 control   // PC6&7 - LED2 and LED3 on Concerto card, PH3 & PF2 - LD4&5 on docking station,   // and PB0, PA6&7 (AFED1,2,3 on AFE board) are config to CM3     // GPIO A1,A3,A4 config jumper inputs, normally high, jumpered low  // a0 and a2 used for PWM on concerto   GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0x05, GPIO_PIN_C_CORE_SELECT);    //bits b1 and 4 for ECAP and OPAEN on concerto   GPIOPinConfigureCoreSelect(GPIO_PORTB_BASE, 0x12, GPIO_PIN_C_CORE_SELECT);  // bits 4-7 only avail on plc module   GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, 0x0F, GPIO_PIN_C_CORE_SELECT);    // bits 4-7 for PGA control on plc module   GPIOPinConfigureCoreSelect(GPIO_PORTD_BASE, 0xF0, GPIO_PIN_C_CORE_SELECT);  // e4 and e5 for uart on plc module    GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);    // f0 and f1 serial eeprom, f2 is PLCD_LED5   GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0x03, GPIO_PIN_C_CORE_SELECT);    // g0-7 avail for CM3   GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);  // GPIODirModeSet(GPIO_PORTG_BASE,0xff,GPIO_DIR_MODE_OUT);    // h3 is PLCD_LED4 for C28   GPIOPinConfigureCoreSelect(GPIO_PORTH_BASE, 0x08, GPIO_PIN_C_CORE_SELECT);    // j0-7 avail for CM3   GPIOPinConfigureCoreSelect(GPIO_PORTJ_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);

  //    /* pull up for ECAP */   GPIOPadConfigSet(GPIO_PORTB_BASE, 0x0A, GPIO_PIN_TYPE_STD_WPU);   //   //    /* pull up for McBSP-A */   GPIOPadConfigSet(GPIO_PORTD_BASE, 0x70, GPIO_PIN_TYPE_STD_WPU);   //      //    /* pull up for UART */   GPIOPadConfigSet(GPIO_PORTE_BASE, 0x30, GPIO_PIN_TYPE_STD_WPU);

// from echo demo     // Enable processor interrupts.     IntMasterEnable();

    // Set GPIO E4 and E5 as UART pins.     GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);     GPIOPinConfigure(GPIO_PE4_U0RX);     GPIOPinConfigure(GPIO_PE5_U0TX);

    // Configure the UART for 115,200, 8-N-1 operation.     UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(SYSTEM_CLOCK_SPEED), 38400,                         (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |                          UART_CONFIG_PAR_NONE));

    // Enable the UART interrupt.     IntRegister(INT_UART0, UARTIntHandler);   // set the priority lower than FreeRTOS //! The hardware priority mechanism will only look at the upper N bits of the //! priority level (where N is 3 for the Concerto family), so any //! prioritization must be performed in those bits.  The remaining bits can be  IntPrioritySet(INT_UART0,160);          IntEnable(INT_UART0); //    UARTIntEnable(UART0_BASE, UART_INT_RX); // | UART_INT_RT);

  // Copy time critical code and Flash setup code to RAM   // This includes the following ISR functions: Timer0IntHandler(), Timer1IntHandler()   //  and InitFlash();   // The  RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart   // symbols are created by the linker. Refer to the device .cmd file.

  MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);

  // Call Flash Initialization to setup flash waitstates   // This function must reside in RAM   FlashInit();

  // Enable processor interrupts.   //IntMasterEnable();

  // assign S0 to S7 of the shared ram for use by the c28 PLC   RamMReqSharedMemAccess((S0_ACCESS | S1_ACCESS | S2_ACCESS | S3_ACCESS | S4_ACCESS | S5_ACCESS | S6_ACCESS | S7_ACCESS),SX_C28MASTER);

  // WKIM: in case of debugging, enable this routine #if 1   // check if the RAM is init   // we use the C2M MSG RAM as indication   // the magic data: 0xdeadbeef   if (c28_init == 1)   {     return;   } #endif

  // wait for c28 initialization   master_ram_init_control_m1_msgram_memories();   master_ram_init_control_L0_L4_memories();

  // C28 boot from flash   IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);

}

 

Then the setup code:

    // Disable clock supply for the watchdog modules     SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);     SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);    

    // Set up the Pin for LED3     GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_7); // | GPIO_PIN_6);     GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, ~0);

    // Set up the Pin for LED2     GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_6);     GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_6, ~0);

    // Set up the Pin for AFELED1     GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0);     GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_0, ~0);

    // Set up the Pin for AFELED2     GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6);     GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6, ~0);

    // Set up the Pin for AFELED3     GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7);     GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_7, ~0);

    // Set up the Pin for PLCDLED4     GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_3);     GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_3, ~0);

    // Set up the Pin for PLCDLED5     GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2);     GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, ~0);         // Config inputs GPIO 1,3,4 (A1, A3, A4     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_1);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_1);     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_3);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_3);     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_4);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_4);      //GPIODirModeSet(GPIO_PORTG_BASE,0xff,GPIO_DIR_MODE_OUT);         // GPIO outputs for Discrete CCU outputs to relay board         // channel 1 Main relays bits 0 - 7     // DOOR 0     GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_0);     GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_0, ~0);  // 1     GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_1);     GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_1,~0);     // 2     GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_2);     GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_2,~0);     // 3     GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_3);     GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_3,~0);     // 4     GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,GPIO_PIN_2);     GPIOPinWrite(GPIO_PORTH_BASE,GPIO_PIN_2,~0);     // 5     GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_7);     GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_7,~0);     // 6     GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE,GPIO_PIN_6);     GPIOPinWrite(GPIO_PORTE_BASE,GPIO_PIN_6,~0);     // 7     GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE,GPIO_PIN_7);     GPIOPinWrite(GPIO_PORTE_BASE,GPIO_PIN_7,~0);              // channel 2 Aux relays bits 0 - 7     // AUX 0     GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_0);     GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,GPIO_PIN_0);     // 1     GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_1);     GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_1,GPIO_PIN_1);     // 2     GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_2);     GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_2,GPIO_PIN_2);     // 3     GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_3);     GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,GPIO_PIN_3);     // 4     GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_3);     GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_3,GPIO_PIN_3);     // 5     GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_5);     GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_5,~0);     // 6     GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_6);     GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_6,~0);     // 7 (tbd)     //GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_0);     //GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,~0);         // channel 3 CTRL relays and optional outputs, bits 0,1, and 2-7     // CTRL0 (EN/DIS)     GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,GPIO_PIN_6);     GPIOPinWrite(GPIO_PORTH_BASE,GPIO_PIN_6, ~0);     // CTRL1 (OPR)     GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,GPIO_PIN_7);     GPIOPinWrite(GPIO_PORTH_BASE,GPIO_PIN_7, ~0);

  // relay discrete inputs 0 - 7     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_1);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_1);

 

 // opto discrete inputs 0 - 7  // RLIN0     GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_0);     GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_0);     // RLIN1     GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_1);     GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_1);     // RLIN2     GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_2);     GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_2);     // RLIN3     GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_3);     GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_3);     // RLIN4     GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_0);     GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_0);  // RLIN5  GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_1);     GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_1);     // RLIN6     GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_2);     GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_2);     // RLIN7     GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_3);     GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_3);         // Opto isolated inputs 0 - 7     // OPIN0     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_1);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_1);     // OPIN1     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_3);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_3);     // OPIN2     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_4);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_4);     // OPIN3     GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_5);     GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_5);     // OPIN4     GPIOPinTypeGPIOInput(GPIO_PORTB_BASE,GPIO_PIN_2);     GPIOPinRead(GPIO_PORTB_BASE, GPIO_PIN_2);     // OPIN5         // OPIN6         // OPIN7    

Sorry about the mess. Do you have an icon to select for software code display?

Thanks,

Pat

This should be easier to read:

  // Disable Protection

  HWREG(SYSCTL_MWRALLOW) =  0xA5A5A5A5;

 

  // Setup main clock tree for 75MHz - M3 and 150MHz - C28x

  SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL |

                       (SYSCTL_SPLLIMULT_M & 0x0F));

  // enable serial uart port 0

  SysCtlPeripheralEnable(SYSCTL_PERIPH_UART0);

  

  // Enable all GPIOs

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);

  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);

 

  // a "1" gives C28 control of GPIO bits, "0" gives CM3 control

  // PC6&7 - LED2 and LED3 on Concerto card, PH3 & PF2 - LD4&5 on docking station,

  // and PB0, PA6&7 (AFED1,2,3 on AFE board) are config to CM3   

 

 

  // a "1" gives C28 control of GPIO bits, "0" gives CM3 control

  // PC6&7 - LED2 and LED3 on Concerto card, PH3 & PF2 - LD4&5 on docking station,

  // and PB0, PA6&7 (AFED1,2,3 on AFE board) are config to CM3  

  // GPIO A1,A3,A4 config jumper inputs, normally high, jumpered low

               // a0 and a2 used for PWM on concerto

  GPIOPinConfigureCoreSelect(GPIO_PORTA_BASE, 0x05, GPIO_PIN_C_CORE_SELECT);

               //bits b1 and 4 for ECAP and OPAEN on concerto

  GPIOPinConfigureCoreSelect(GPIO_PORTB_BASE, 0x12, GPIO_PIN_C_CORE_SELECT);

               // bits 4-7 only avail on plc module

  GPIOPinConfigureCoreSelect(GPIO_PORTC_BASE, 0x0F, GPIO_PIN_C_CORE_SELECT);

               // bits 4-7 for PGA control on plc module

  GPIOPinConfigureCoreSelect(GPIO_PORTD_BASE, 0xF0, GPIO_PIN_C_CORE_SELECT);

               // e4 and e5 for uart on plc module 

  GPIOPinConfigureCoreSelect(GPIO_PORTE_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);

               // f0 and f1 serial eeprom, f2 is PLCD_LED5

  GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0x03, GPIO_PIN_C_CORE_SELECT);

               // g0-7 avail for CM3

  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);

 //           GPIODirModeSet(GPIO_PORTG_BASE,0xff,GPIO_DIR_MODE_OUT);

               // h3 is PLCD_LED4 for C28

  GPIOPinConfigureCoreSelect(GPIO_PORTH_BASE, 0x08, GPIO_PIN_C_CORE_SELECT);

               //            j0-7 avail for CM3

  GPIOPinConfigureCoreSelect(GPIO_PORTJ_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);

 

  //    /* pull up for ECAP */

  GPIOPadConfigSet(GPIO_PORTB_BASE, 0x0A, GPIO_PIN_TYPE_STD_WPU);

  //

  //    /* pull up for McBSP-A */

  GPIOPadConfigSet(GPIO_PORTD_BASE, 0x70, GPIO_PIN_TYPE_STD_WPU);

  //   

  //    /* pull up for UART */

  GPIOPadConfigSet(GPIO_PORTE_BASE, 0x30, GPIO_PIN_TYPE_STD_WPU);

 

 

// from echo demo

    // Enable processor interrupts.

    IntMasterEnable();

 

    // Set GPIO E4 and E5 as UART pins.

    GPIOPinTypeUART(GPIO_PORTE_BASE, GPIO_PIN_4 | GPIO_PIN_5);

    GPIOPinConfigure(GPIO_PE4_U0RX);

    GPIOPinConfigure(GPIO_PE5_U0TX);

 

    // Configure the UART for 115,200, 8-N-1 operation.

    UARTConfigSetExpClk(UART0_BASE, SysCtlClockGet(SYSTEM_CLOCK_SPEED), 38400,

                        (UART_CONFIG_WLEN_8 | UART_CONFIG_STOP_ONE |

                         UART_CONFIG_PAR_NONE));

 

    // Enable the UART interrupt.

    IntRegister(INT_UART0, UARTIntHandler);

  // set the priority lower than FreeRTOS

//! The hardware priority mechanism will only look at the upper N bits of the

//! priority level (where N is 3 for the Concerto family), so any

//! prioritization must be performed in those bits.  The remaining bits can be

               IntPrioritySet(INT_UART0,160); 

   

    IntEnable(INT_UART0);

//    UARTIntEnable(UART0_BASE, UART_INT_RX); // | UART_INT_RT);

 

  // Copy time critical code and Flash setup code to RAM

  // This includes the following ISR functions: Timer0IntHandler(), Timer1IntHandler()

  //  and InitFlash();

  // The  RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart

  // symbols are created by the linker. Refer to the device .cmd file.

 

  MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);

 

  // Call Flash Initialization to setup flash waitstates

  // This function must reside in RAM

  FlashInit();

 

  // Enable processor interrupts.

  //IntMasterEnable();

 

  // assign S0 to S7 of the shared ram for use by the c28 PLC

  RamMReqSharedMemAccess((S0_ACCESS | S1_ACCESS | S2_ACCESS | S3_ACCESS | S4_ACCESS | S5_ACCESS | S6_ACCESS | S7_ACCESS),SX_C28MASTER);

 

  // WKIM: in case of debugging, enable this routine

#if 1

  // check if the RAM is init

  // we use the C2M MSG RAM as indication

  // the magic data: 0xdeadbeef

  if (c28_init == 1)

  {

    return;

  }

#endif

 

  // wait for c28 initialization

  master_ram_init_control_m1_msgram_memories();

  master_ram_init_control_L0_L4_memories();

 

  // C28 boot from flash

  IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_FLASH);

 

 

}

 

And the setup code:

    // Disable clock supply for the watchdog modules

    SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG1);

    SysCtlPeripheralDisable(SYSCTL_PERIPH_WDOG0);

   

 

    // Set up the Pin for LED3

    GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_7); // | GPIO_PIN_6);

    GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_7, ~0);

 

    // Set up the Pin for LED2

    GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_6);

    GPIOPinWrite(GPIO_PORTC_BASE, GPIO_PIN_6, ~0);

 

    // Set up the Pin for AFELED1

    GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0);

    GPIOPinWrite(GPIO_PORTB_BASE, GPIO_PIN_0, ~0);

 

    // Set up the Pin for AFELED2

    GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_6);

    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_6, ~0);

 

    // Set up the Pin for AFELED3

    GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE, GPIO_PIN_7);

    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_7, ~0);

 

    // Set up the Pin for PLCDLED4

    GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTH_BASE, GPIO_PIN_3, ~0);

 

    // Set up the Pin for PLCDLED5

    GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, ~0);

   

    // Config inputs GPIO 1,3,4 (A1, A3, A4

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_1);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_1);

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_3);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_3);

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_4);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_4);

   

               //GPIODirModeSet(GPIO_PORTG_BASE,0xff,GPIO_DIR_MODE_OUT);

   

    // GPIO outputs for Discrete CCU outputs to relay board

   

    // channel 1 Main relays bits 0 - 7

    // DOOR 0

    GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_0);

    GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_0, ~0);

               // 1

    GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_1);

    GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_1,~0);

    // 2

    GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_2,~0);

    // 3

    GPIOPinTypeGPIOOutput(GPIO_PORTJ_BASE,GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTJ_BASE,GPIO_PIN_3,~0);

    // 4

    GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTH_BASE,GPIO_PIN_2,~0);

    // 5

    GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_7);

    GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_7,~0);

    // 6

    GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE,GPIO_PIN_6);

    GPIOPinWrite(GPIO_PORTE_BASE,GPIO_PIN_6,~0);

    // 7

    GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE,GPIO_PIN_7);

    GPIOPinWrite(GPIO_PORTE_BASE,GPIO_PIN_7,~0);

                  

   

    // channel 2 Aux relays bits 0 - 7

    // AUX 0

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_0);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,GPIO_PIN_0);

    // 1

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_1);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_1,GPIO_PIN_1);

    // 2

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_2,GPIO_PIN_2);

    // 3

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,GPIO_PIN_3);

    // 4

    GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_3,GPIO_PIN_3);

    // 5

    GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_5);

    GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_5,~0);

    // 6

    GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE,GPIO_PIN_6);

    GPIOPinWrite(GPIO_PORTB_BASE,GPIO_PIN_6,~0);

    // 7 (tbd)

    //GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_0);

    //GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,~0);

   

    // channel 3 CTRL relays and optional outputs, bits 0,1, and 2-7

    // CTRL0 (EN/DIS)

    GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,GPIO_PIN_6);

    GPIOPinWrite(GPIO_PORTH_BASE,GPIO_PIN_6, ~0);

    // CTRL1 (OPR)

    GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE,GPIO_PIN_7);

    GPIOPinWrite(GPIO_PORTH_BASE,GPIO_PIN_7, ~0);

 

               // relay discrete inputs 0 - 7

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_1);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_1);

 

 

 

               // opto discrete inputs 0 - 7

               // RLIN0

    GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_0);

    GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_0);

    // RLIN1

    GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_1);

    GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_1);

    // RLIN2

    GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_2);

    GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_2);

    // RLIN3

    GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_3);

    GPIOPinRead(GPIO_PORTD_BASE, GPIO_PIN_3);

    // RLIN4

    GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_0);

    GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_0);

               // RLIN5

               GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_1);

    GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_1);

    // RLIN6

    GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_2);

    GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_2);

    // RLIN7

    GPIOPinTypeGPIOInput(GPIO_PORTE_BASE,GPIO_PIN_3);

    GPIOPinRead(GPIO_PORTE_BASE, GPIO_PIN_3);

   

    // Opto isolated inputs 0 - 7

    // OPIN0

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_1);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_1);

    // OPIN1

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_3);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_3);

    // OPIN2

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_4);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_4);

    // OPIN3

    GPIOPinTypeGPIOInput(GPIO_PORTA_BASE,GPIO_PIN_5);

    GPIOPinRead(GPIO_PORTA_BASE, GPIO_PIN_5);

    // OPIN4

    GPIOPinTypeGPIOInput(GPIO_PORTB_BASE,GPIO_PIN_2);

    GPIOPinRead(GPIO_PORTB_BASE, GPIO_PIN_2);

    // OPIN5

   

    // OPIN6

   

    // OPIN7

Pat,

from your source comments above, looks like you are using below code to configure IO for master, can you clarify?

               // g0-7 avail for CM3

  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0x00, GPIO_PIN_C_CORE_SELECT);

if yes, then it might not works depending on what was the prev. configuration of the IO. To assign all Port G IOs back to Master you should use

  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_M_CORE_SELECT);

Can you verufy if your code is affected by the above?

 

Best Regards

Santosh

I made the following changes. With this, I lost bit 2, which previously worked. Now none of the 4 bits in the G port output.

               // f0 and f1 serial eeprom, f2 is PLCD_LED5

  GPIOPinConfigureCoreSelect(GPIO_PORTF_BASE, 0x03, GPIO_PIN_C_CORE_SELECT);

               // g0-7 avail for CM3

  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0x00, GPIO_PIN_M_CORE_SELECT);

 //           GPIODirModeSet(GPIO_PORTG_BASE,0xff,GPIO_DIR_MODE_OUT);

               // h3 is PLCD_LED4 for C28

  GPIOPinConfigureCoreSelect(GPIO_PORTH_BASE, 0x08, GPIO_PIN_C_CORE_SELECT);  

 

 

GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,0xff); //GPIO_PIN_0);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,0x1);

    // 1

    //GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_1);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_1,0x1);

    // 2

    //GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_2,0x1);

    // 3

    //GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,0x1);

 

Pat Harris said:

GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0x00, GPIO_PIN_M_CORE_SELECT);

I believe that is still wrong, you should be using GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_M_CORE_SELECT);?

 

Best Regards

Santosh

I went back to my previous configuration and still can't get bit 2 to work. Port B, pins 3,5,and 6 do work???

Pat

 

Pat,

can you first confirm if Port G issue with your code is cleared now, does it work with above fix suggested?

Port B should work as well.

 

Best Regards

Santosh

Also, in another group, called DOOR, I cannot get PortH, pin2, Port B, pin 7, and Port E, pin 6 to work. Could this be a problem with the Concerto module that I am using, the F28M35xx ISO controlCARD???

Thanks,

Pat

 

Santosh,

I don't mean a specific module, but the module design or assembly. I have tried this on three F28M35xx modules and got the same result.

Pat

 

Pat,

PB7 has a lock on it as defined in device TRM (system control and GPIO sections) , you need to first unlock it to use it as normal IO.

I guess all the other IO should be having similar configuration issues as PortG had in your code snippet above, can you check and confirm?

 

Best Regards
Santosh

I did try this, and still no change.

Pat

 

what about Port G, was that fixed? I believe it was PORTG problem we started this thread with, were you able to toggle Port G after above suggested code change? if not, can we continue on that debug and make sure why it is not working.

All these modules are tested so they should work, can you first close the PortG issue? If you see the same result on multiple hardware, it could be also because you are running the same software with same error on all these boards. We can take a look and help you out with other ports, to see if there is any problem, one by one.

 

Best Regards
Santosh

 

Santosh,

Here is my setup for port G. Now none of the bits respond.

      // g0-7 avail for CM3

  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_M_CORE_SELECT);

 

 

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_0);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,0x1);

    // 1

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_1);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_1,0x1);

    // 2

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_2,0x1);

    // 3

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,0x1);

Pat,

you should be using below, I have highlighted the corrections for ease.

 // g0-7 avail for CM3

  GPIOPinConfigureCoreSelect(GPIO_PORTG_BASE, 0xFF, GPIO_PIN_M_CORE_SELECT);

   GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_0);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_0,GPIO_PIN_0);

    // 1

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_1);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_1,GPIO_PIN_1);

    // 2

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_2);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_2,GPIO_PIN_2);

    // 3

    GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE,GPIO_PIN_3);

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,GPIO_PIN_3);

I've mentioned this in one of hte posts above, and to set a pin 0, for ex: to set PG3 IO to '0', you should use below.

    GPIOPinWrite(GPIO_PORTG_BASE,GPIO_PIN_3,~GPIO_PIN_3);

can you correct your code and let me know if PORTG works now?

 

Best Regards

Santosh

 

Pat,

I'm glad you found the problem. But the code I listed above is the right way to toggle an IO on master subsystem using driver lib functions.

 

Best Regards
Santosh