Hi,
I have a strange behaviour. I'm using the TMS320F2802x. If I link the code of the ISR to RAM it is going slower than if it's partly placed in flash.
I have an interrupt routine which is triggered from end of conversion ADC. In the routine I go to an assembler function (af()) and after that to a C++ function (cf()). In the af() I use the Digital Power Library Control blocks from TI.
First it was defined that the cf() was done in RAM and for the af() nothing was defined. And so the af() was done in flash. I saw that with the JTAG emulator in the disassembly view.
Then I defined that the af() is also done in RAM. For that I had also to adapt the linker cmd file. Length of PRAML0 has to be set to 0x00D0. And now the cylce time increase.
I expected that I get more performance if my ISR runs complete in RAM because of 0-wait. Is that wrong?
Maybe it have to do with the space. If I increase the length of PRAML0 to 0x00D0, DRAML0 goes small.
Below I copied parts of the linker cmd file.
I have now two questions:
- Does I get more performance if I copy the code to RAM?
- If yes: What could be the problem that my code runs not faster?
Kind regards
Matt
MEMORY
{
PAGE 0: /* Program Memory */
PRAML0 : origin = 0x008000, length = 0x000B00 /* on-chip RAM block L0 */
....
PAGE 1 : /* Data Memory */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x0003F7 /* on-chip RAM block M1 */
DRAML0 : origin = 0x008B00, length = 0x0004F7 /* on-chip RAM block L0 */
....
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA | FLASHC | FLASHD PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = PRAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
ramfuncsB : LOAD = FLASHB,
RUN = PRAML0,
LOAD_START(_RamfuncsBLoadStart),
LOAD_END(_RamfuncsBLoadEnd),
RUN_START(_RamfuncsBRunStart),
PAGE = 0
ramfuncsC : LOAD = FLASHC,
RUN = PRAML0,
LOAD_START(_RamfuncsCLoadStart),
LOAD_END(_RamfuncsCLoadEnd),
RUN_START(_RamfuncsCRunStart),
PAGE = 0
csmpasswds : > CSM_PWL_P0 PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
/*.stack : > RAMM0 PAGE = 1*/
.stack : > RAMM0,
RUN_START(_HWI_STKBOTTOM),
RUN_END(_HWI_STKTOP),
PAGE = 1
.ebss : > DRAML0 PAGE = 1
.esysmem : > DRAML0 PAGE = 1
.sysmem : > RAMM1 PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
SECTIONS
{
/* controlSUITE Sections */
ADCDRV_1ch_Section : > DRAML0 PAGE = 1
...
}