Piccolo Comparator Block with Ramp generator

Thomas,

1) I spoke with an engineer who has used the ramp generator feature.  The PWMSYNCx signal is independent from the other PWM sync signals (PWMxSYNCI, PWMxSYNCO).  The PWMSYNCx signal is generated by PWMx on every TBCTR=Zero event.

2) It means that the PWMSYNC signal needs to be longer than SYSCLK in order to guarantee that the ramp generator detects it.  Since the PWMSYNC signal can come from the Comparator, it does not necessarily mean the PWM has to run at SYSCLK/2, just that the sync signal is longer than SYSCLK.  If you are using a PWMSYNC signal generated by a PWM module, this criteria is met.

I hope this answers your questions.

Regards,
Daniel

Thomas Hattermann said:

in SPRUGE5F I can read, that the ramp generator is reloaded with 'PWMSYNx'.
In the ePWM sheet there are the signals 'PWMxSYNCI' and 'PWMxSYNCO'. which signal is used?

1) I spoke with an engineer who has used the ramp generator feature.  The PWMSYNCx signal is independent from the other PWM sync signals (PWMxSYNCI, PWMxSYNCO).  The PWMSYNCx signal is generated by PWMx on every TBCTR=Zero event.

Daniel Chang said:

1) I spoke with an engineer who has used the ramp generator feature.  The PWMSYNCx signal is independent from the other PWM sync signals (PWMxSYNCI, PWMxSYNCO).  The PWMSYNCx signal is generated by PWMx on every TBCTR=Zero event.

Ok, the PWMSYNCx signal always comes from the PWM on TBCTR=Zero. So it is always synchronous and with a length of one clock.

Daniel Chang said:

2) It means that the PWMSYNC signal needs to be longer than SYSCLK in order to guarantee that the ramp generator detects it.  Since the PWMSYNC signal can come from the Comparator, it does not necessarily mean the PWM has to run at SYSCLK/2, just that the sync signal is longer than SYSCLK.  If you are using a PWMSYNC signal generated by a PWM module, this criteria is met.

From comparator? Sorry I don't understand. It comes on TBCTR=Zero.

Hello,

What's about the not documented bit 'ePWM[n].HRPCTL.bit.PWMSYNCSEL'? The Power library use this bit with the comment: "// PWM SYNC generated at CTR = ZRO for synchronizing internal ramp".

Thanks Thomas

Hello,

I found the answer about the sync signal in SPRUGE8E at page 37:

PWMSYNCSEL:

PWMSYNC Source Select Bit
This bit selects the source for the PWMSYNC signal.
The PWMSYNC signal is used by external modules (such as COMP+DAC) for synchronizing
timing to the selected ePWM module.
Note: This bit is not used for high-resolution period control.
0 PWMSYNC is generated by TBCTR = PRD pulse.
1 PWMSYNC is generated by TBCTR = 0 pulse.

So if the only sync can come from PWM Module the open question is:

What does this mean (SPRUGE5F Page 47):
'The PWMSYNC signal width must be greater than SYSCLK to ensure that the ramp generator is able to detect the PWMSYNC signal.'
Does it mean PWM module must work with SYSCLK/2?

Thanks for your help.

Thomas Hattermann

hello, 

i m pradeep and i m working on synchronization of epwm on piccolo f28069NPA so my problem in code i m generating ewpm on interrupt isr function so if i m using interrupt isr i m unable to do synchronization properly means to say i can lock master piccolo pluse with slave  piccolo pulse but  i m unable tolock in phase shift both are not starting with zero degree... when i m connecting synco of master with synci of slave then at that insistent both pulses are getting lock but the phase is not same as i mentioned with zero phase in code 

if i remove and reconnect synci and synco then again i m getting new phase shift....  

and as from above discussion i came to know one thing to do synchronization we need to keep SYSCLK/2 right but i m using SYSCLK/1 is it makes any difference in piccolo f28096

waiting for reply,

     

Hi pradeep kumar ama,

my testresults are:

connecting 2 PWMs internal with SYNCO on CTR=0 results in a delay of 2 clocks. Using SYNCO on CTR=period has still one clock delay between the PWMs.

So you have to set the phase register.

Thomas Hattermann

thanks for reply,

i m setting 1)tbprd=2964 and cpma=296 so for one clock cycle what is value i need to feed in to phase register...

2)  said to feed CTR=period means tbprd right

  

Hi radeep kumar ama,

1) tbphs = 1

tbctl.PHSEN = 1

2 ) right

hi thanks for reply,

still im facing the same problem

this is the setting i m giving for slave piccolo 

// Setup TBCLK
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period 1482 TBCLKs
EPwm2Regs.TBPHS.half.TBPHS =1;

EPwm2Regs.TBCTR = EPWM2_TIMER_TBPRD; // Clear counter

// Set Compare values
EPwm2Regs.CMPA.half.CMPA = EPWM2_CMPA; // Set compare A value
EPwm2Regs.CMPB = EPWM2_CMPB;
// Setup counter mode
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT/2
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

//#################################################################
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
EPwm2Regs.TBCTL.bit.SWFSYNC=1;
EPwm2Regs.TBCTL.bit.PHSDIR=1;
//######################################################################

// Setup shadowing
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // Load on Zero
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

// Set actions
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on event A, up
// count
EPwm2Regs.AQCTLA.bit.CAD =AQ_CLEAR; // Clear PWM1A on event A,
// down count

EPwm2Regs.AQCTLB.bit.CBU = AQ_SET; // Set PWM1B on event B, up
// count
EPwm2Regs.AQCTLB.bit.CBD = AQ_CLEAR; // Clear PWM1B on event B,
// down count

// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event

// Information this example uses to keep track
// of the direction the CMPA/CMPB values are
// moving, the min and max allowed values and
// a pointer to the correct ePWM registers
epwm2_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA &
epwm2_info.EPwm_CMPB_Direction = EPWM_CMP_UP;
epwm2_info.EPwmTimerIntCount = 1; // one on the interrupt counter
epwm2_info.EPwm2RegHandle = &EPwm2Regs; // Set the pointer to the
// ePWM module
epwm2_info.EPwmCMPA = EPWM2_CMPA; // Setup CMPA  148
epwm2_info.EPwmCMPB = EPWM2_CMPB;// Setup CMPB  148

 i attaching photos also when i m reconnecting the synco t synci then the pulses are locked at different angles not at zero..

hi,

i have one doubt that this epwm what i m planning is available in excel so can i upload that excel file  in to my program

with rise time and fall time and pulses width and angle details 

Hello Thomas ,

I guess you have solved the problem,

According to your and other's description,

I set PWMSYNCSEL=0,

and ensure the PWMSYNC signal width must be greater than SYSCLK

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; 
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV2;

But It seems that I still can not trigger the ramp generator,

Is there something I have missed?

Enclose part of my program

————————————————————————————

SysCtrlRegs.PCLKCR3.bit.COMP1ENCLK = 1;   // Enable clock to the Comparator 1 block
Comp1Regs.COMPCTL.bit.COMPDACEN = 1;   // Power up Comparator 1 locally
Comp1Regs.COMPCTL.bit.COMPSOURCE = 0;  // Connect the inverting input to the internal DAC

Comp1Regs.RAMPMAXREF_SHDW = 60000;
Comp1Regs.RAMPDECVAL_SHDW = 10;

Comp1Regs.DACCTL.bit.DACSOURCE = 1;  // DAC controlled by ramp generator
Comp1Regs.DACCTL.bit.RAMPSOURCE = 0 ; // PWMSYNC1

SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;

//// EPWM ///

EPwm1Regs.TBPRD = 2000; // Set timer period
EPwm1Regs.TBPHS.all = 1; // Phase is 0
EPwm1Regs.TBCTR = 0x0000;

// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = 1;

EPwm1Regs.TBCTL.bit.SYNCOSEL = 0; 

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2;   
EPwm1Regs.TBCTL.bit.CLKDIV = 0;   
// TBCLK = SYSCLKOUT / (HSPCLKDIV × CLKDIV)
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;   // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

// Setup compare
EPwm1Regs.CMPA.half.CMPA = 1000;

EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on CAU
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on CAD

EPwm1Regs.HRPCTL.bit.PWMSYNCSEL= 1 ;

——————————————————————————————————————

hope you can get my question 

Thank you,

Yang XU.

 

 

 

Thanks for reply,

The codes are actually right,

I maked some mistakes in other aspects.

Thanks,

Yang Xu

Hi,
just my experiences:
- Ramp-PWMSYNC is on CTR = 0 and independent from every other sync
- Ramp-PWMSYNC is not generated in UP- or UPDOWN-countmode when Phaseloading is enabled
- perhaps it is never generated in UPDOWN-countmode, but didn't investigate this further
- in DOWN-countmode everthing seems to work as expected, even Phaseloading.

can someone confirm this?

Hi,

PWMSYNC is independent from other SYNC mechanism used to synchronize time base of PWM.
This PWMSYNC signal is used by modules (such as COMP+DAC) for syncing timing to the selected EPWM mdoule.
It should work in all counter modes depending on what you choose as source for PWMSYNC via PWMSYNCSEL bit in HRPCTL register.

-Bharathi.