I'm programming the CLA on the TMX320F28069 control stick. The application running on the CLA triggers the ETFRC register in ePWM4.
Epwm4 is configured, running and has interrupts enabled.
Forcing the interrupt via the ETFRC from within the CLA works fine and the ETFLG register contains 0x1 to signal the interrupt is generated.
Debugging from the C28x and setting (ETFRC) and clearing (ETCLR) the ETFLG manually does not generate an interrupt, but also sets the ETFLG register to 0x01.
The generated interrupt latched by ETFLG register does not generate an interrupt in the PIEFR3 register
I'm using the following register settings, for ePWM4 which does not use HRPWM and the Deadband or Digital compare.
ePWM4
TBCTL 0x2036 Time Base Control Register [Memory Mapped]
TBSTS 0x0002 Time Base Status Register [Memory Mapped]
TBPHS 0x00020000 Union of TBPHS:TBPHSHR [Memory Mapped]
TBCTR 0x0526 Time Base Counter [Memory Mapped]
TBPRD 0x0708 Time Base Period register set [Memory Mapped]
TBPRDHR 0x0000 Time Base Period High Res Register [Memory Mapped]
CMPCTL 0x0000 Compare control [Memory Mapped]
CMPA 0xFFFF0000 Union of CMPA:CMPAHR [Memory Mapped]
CMPB 0x0000 Compare B reg [Memory Mapped]
AQCTLA 0x0090 Action qual output A [Memory Mapped]
AQCTLB 0x0000 Action qual output B [Memory Mapped]
AQSFRC 0x0000 Action qual SW force [Memory Mapped]
AQCSFRC 0x0001 Action qualifier continuous SW force [Memory Mapped]
DBCTL 0x0000 Dead-band control [Memory Mapped]
DBRED 0x0000 Dead-band rising edge delay [Memory Mapped]
DBFED 0x0000 Dead-band falling edge delay [Memory Mapped]
TZSEL 0x0001 Trip zone select [Memory Mapped]
TZDCSEL 0x0000 Trip zone digital comparator select [Memory Mapped]
TZCTL 0x000E Trip zone control [Memory Mapped]
TZEINT 0x0000 Trip zone interrupt enable [Memory Mapped]
TZFLG 0x0000 Trip zone interrupt flags [Memory Mapped]
TZCLR 0x0000 Trip zone clear [Memory Mapped]
TZFRC 0x0000 Trip zone force interrupt [Memory Mapped]
ETSEL 0000000000001000 (Binary) Event trigger selection [Memory Mapped]
ETPS 0x1101 Event trigger pre-scaler [Memory Mapped]
ETFLG 0x0001 Event trigger flags [Memory Mapped]
ETCLR 0x0000 Event trigger clear [Memory Mapped]
ETFRC 0x0000 Event trigger force [Memory Mapped]
PCCTL 0x0000 PWM chopper control [Memory Mapped]
HRCNFG 0x0000 HRPWM Config Reg [Memory Mapped]
HRPCTL 0x0000 High Resolution Period Control [Memory Mapped]
TBPRDM 0x07080000 Union of TBPRD:TBPRDHR mirror registers [Memory Mapped]
CMPAM 0xFFFF0000 Union of CMPA:CMPAHR mirror registers [Memory Mapped]
DCTRIPSEL 0x0000 Digital Compare Trip Select [Memory Mapped]
DCACTL 0x0000 Digital Compare A Control [Memory Mapped]
DCBCTL 0x0000 Digital Compare B Control [Memory Mapped]
DCFCTL 0x0000 Digital Compare Filter Control [Memory Mapped]
DCCAPCTL 0x0000 Digital Compare Capture Control [Memory Mapped]
DCFOFFSET 0x0000 Digital Compare Filter Offset [Memory Mapped]
DCFOFFSETCNT 0x0000 Digital Compare Filter Offset Counter [Memory Mapped]
DCFWINDOW 0x0000 Digital Compare Filter Window [Memory Mapped]
DCFWINDOWCNT 0x0000 Digital Compare Filter Window Counter [Memory Mapped]
DCCAP 0x0000 Digital Compare Filter Counter Capture [Memory Mapped]
The PIE is configured as follows and captured the PIE after the ETFLG register is set
PIE
PIECTRL 0x0001 PIE, Control Register [Memory Mapped]
PIEACK 0x0000 PIE, Acknowledge Register [Memory Mapped]
PIEIER1 0x0000 PIE, INT1 Group Enable Register [Memory Mapped]
PIEIFR1 0x0001 PIE, INT1 Group Flag Register [Memory Mapped]
PIEIER2 0x0000 PIE, INT2 Group Enable Register [Memory Mapped]
PIEIFR2 0x0000 PIE, INT2 Group Flag Register [Memory Mapped]
PIEIER3 0x0008 PIE, INT3 Group Enable Register [Memory Mapped]
PIEIFR3 0x0000 PIE, INT3 Group Flag Register [Memory Mapped]
PIEIER4 0x0000 PIE, INT4 Group Enable Register [Memory Mapped]
PIEIFR4 0x0000 PIE, INT4 Group Flag Register [Memory Mapped]
PIEIER5 0x0000 PIE, INT5 Group Enable Register [Memory Mapped]
PIEIFR5 0x0000 PIE, INT5 Group Flag Register [Memory Mapped]
PIEIER6 0x0000 PIE, INT6 Group Enable Register [Memory Mapped]
PIEIFR6 0x0000 PIE, INT6 Group Flag Register [Memory Mapped]
PIEIER7 0x0000 PIE, INT7 Group Enable Register [Memory Mapped]
PIEIFR7 0x0000 PIE, INT7 Group Flag Register [Memory Mapped]
PIEIER8 0x0000 PIE, INT8 Group Enable Register [Memory Mapped]
PIEIFR8 0x0000 PIE, INT8 Group Flag Register [Memory Mapped]
PIEIER9 0x0000 PIE, INT9 Group Enable Register [Memory Mapped]
PIEIFR9 0x0000 PIE, INT9 Group Flag Register [Memory Mapped]
PIEIER10 0x0000 PIE, INT10 Group Enable Register [Memory Mapped]
PIEIFR10 0x0001 PIE, INT10 Group Flag Register [Memory Mapped]
PIEIER11 0x0000 PIE, INT11 Group Enable Register [Memory Mapped]
PIEIFR11 0x0001 PIE, INT11 Group Flag Register [Memory Mapped]
PIEIER12 0x0000 PIE, INT12 Group Enable Register [Memory Mapped]
PIEIFR12 0x0000 PIE, INT12 Group Flag Register [Memory Mapped]
Question: What could cause the interrupt to not be visible in the PIEFR3 register, and what could i check?
Thanks in advance,
Regards Rob
