Seaching for FCLK I have found the following:
Frank Bormann wrote the following post at Feb 9, 2012 1:36 AM:
in your first post you showed register ADCTRL3 to be 0x00E0. This init value will set the ADC's FCLK = HSPCLK, which is far above the maximum of 25MHz. Where in your code do you initialize bits 4-1 of ADCTRL3? Also, SPRU812 recommends to keep FCLK below 12.5MHz to reduce the impact of the integral nonlinearity error (INL).
Is this really stated in SPRU812? I am going cross-eyed reading and re-reading this document, but find very few refs to Fclk, and none specifying a safe maximum.
I would like to know where the 12.5 recommendation is documented? I will need something to prove to others that going faster is not advisable.
Thanks.
