Other Parts Discussed in Thread: TMS320F28069
Hi ,
I am trying to transmit a message from a TMS320F28069 experimental kit to another one of the same kind.
1.I have written a code for transmission on one dsp and that for reception at the other. The 230QD transceiver is used. There are 120 ohm resistors connected at the 2 ends of a shielded cable which connects the 2 DSPs. I am sensing the voltage through ADC2 and is voltage there exceeds 1.5V, I need to send messages through CAN.I am sending messages through mailbox5 only. I can see the message(CANMDL and CANMDH contents) sent on the watch window.But there is no signal across the CAN lines. Can someone help me on this?
2. The BRPreg value given in ecanback2back eg is 1 which corresponds to 40MHz operation. Won't this value be too high for CAN to operate when I am trying to transmit data to another node? I also tried with BRPreg = 19. But I did not get any signal on the line.
3. When the receive pgm gets executed, the CANRMP doesnot get set to 0xFFFFFFFF. Hence it goes into an infinite loop. I tried to force CANRMP to be equal to 0xFFFFFFFF in the pgm but it remains at 0x00000000. Also, the can mailbox contents show some erronoeus values.
I am pasting both the codes here. Pls help me urgently as I have a very tight deadline.
#include "PeripheralHeaderIncludes.h"
#include "F2806x_EPwm_defines.h" // useful defines for initialization
#include "DSP28x_Project.h" // Device Headerfile and Examples Include File
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// FUNCTION PROTOTYPES
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
void DeviceInit(void);
void InitFlash();
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// VARIABLE DECLARATIONS - GENERAL
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// Used for running BackGround in flash, and ISR in RAM
extern Uint16 RamfuncsLoadStart, RamfuncsLoadEnd, RamfuncsRunStart;
Uint16 LoopCount=0;
Uint16 i,endcount=0;
Uint16 j,count=0;
Uint32 temp,ErrorCount=0;//ecan
Uint16 Voltage_ADC2;
float duty_cycle_A = 1666;
Uint16 duty_cycle_B=2000;
void main(void)
{
Uint16 i = 0;
struct ECAN_REGS ECanaShadow;
DeviceInit();
#ifdef FLASH
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
InitFlash(); // Call the flash wrapper init function
#endif //(FLASH)
//=================================
// INITIALISATION - Peripherals
//=================================
DINT;
IER = 0x0000;
IFR = 0x0000;
EALLOW;
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; // Power up band gap
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; // Power up reference
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; // Power up rest of ADC
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; // set timming to 13cycles as required by ADC module
for(i=0; i<5000; i++){} // wait 60000 cycles = 1ms (each iteration is 12 cycles)
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; // create int pulses 1 cycle prior to output latch
// Configure ADC
AdcRegs.ADCSOC0CTL.bit.CHSEL = 2; //set SOC0 channel select to ADCINA2
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 5; //set SOC0 start trigger on EPWM1A, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC0CTL.bit.ACQPS = 8; //set SOC0 S/H Window to 8 ADC Clock Cycles, (8 ACQPS plus 1)
EDIS;
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 500; // Set compare A value, duty cycle 50% initially
EPwm1Regs.TBPRD = 1000; // Set period, 80kHz when PLL is set to 0x10 (80MHz)
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
//====================================================================
// PWM DAC output configuration
//====================================================================
// Time-base registers
EPwm1Regs.TBPHS.all = 0; // Time-Base Phase Register
EPwm1Regs.TBCTR = 0; // Time-Base Counter Register
EPwm1Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // Set Immediate load
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count-up mode: used for asymmetric PWM
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM2A on Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on event A, up count
EALLOW;
GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0; // Enable pull-up for GPIO30 (CANRXA)
GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0; // Enable pull-up for GPIO31 (CANTXA)
GpioCtrlRegs.GPADIR.bit.GPIO30 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO31 = 1;
GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1; // Configure GPIO30 for CANRXA operation
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1; // Configure GPIO31 for CANTXA operation
EDIS;
for(;;) //infinite loop
{
LoopCount++;
Voltage_ADC2 = AdcResult.ADCRESULT0; //add Voltage_ADC2 to watch window
voltage = (AdcResult.ADCRESULT0*3.3)/4095;
if(voltage>1.5)
{
EALLOW;
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;
ECanaRegs.CANTA.all = 0xFFFFFFFF; /* Clear all TAn bits */
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
/* Configure bit timing parameters for eCANA*/
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
ECanaShadow.CANBTC.bit.BRPREG = 1;
ECanaShadow.CANBTC.bit.TSEG2REG = 4;
ECanaShadow.CANBTC.bit.TSEG1REG = 13;
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..
/* Disable all Mailboxes */
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
ECanaMboxes.MBOX5.MSGID.all = 0x00140000; // Std identifier
ECanaRegs.CANME.all = 0xFFFFFFFF;
ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
EALLOW;
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.bit.MD5 = 0;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
EALLOW;
ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX5.MDL.all = 0x00140000;
ECanaMboxes.MBOX5.MDH.all = 0x89ABCDEF;
ECanaRegs.CANMIM.all = 0xFFFFFFFF;
EALLOW;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.STM = 0; // Configure CAN for self-test mode
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
EDIS;
ECanaRegs.CANTRS.all = 0x00000020;
while(ECanaRegs.CANTA.all == 0x00000020){}
ECanaRegs.CANTA.all == 0x00000020;
endcount++;
}
else
{
temp++;
}
}
}
The receive code on the second DSP is as follows
#include "PeripheralHeaderIncludes.h"
#include "F2806x_EPwm_defines.h" // useful defines for initialization
#include "DSP28x_Project.h"
void DeviceInit(void);
void InitFlash();
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
void mailbox_check(int32 T1, int32 T2, int32 T3);
void mailbox_read(int16 i);
extern Uint16 RamfuncsLoadStart, RamfuncsLoadEnd, RamfuncsRunStart;
Uint16 LoopCount,i,j,temp=0;
Uint32 ErrorCount;
Uint32 PassCount;
Uint32 MessageReceivedCount;
Uint32 RXCOUNT;
Uint32 TestMbox1 = 0;
Uint32 TestMbox2 = 0;
Uint32 TestMbox3 = 0;
void main()
{
struct ECAN_REGS ECanaShadow;
DeviceInit();
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.SCB = 1;
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaRegs.CANRMP.all = 0xFFFFFFFF; /* Clear all RMPn bits */
ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
do
{
ECanaShadow.CANES.all = ECanaRegs.CANES.all;
}while(ECanaShadow.CANES.bit.CCE == 0); // Wait for CCE bit to be set..
ECanaShadow.CANBTC.all = 0;
ECanaShadow.CANBTC.bit.BRPREG = 1;
ECanaShadow.CANBTC.bit.TSEG2REG = 4;
ECanaShadow.CANBTC.bit.TSEG1REG = 13;
ECanaShadow.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;
ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
EDIS;
ECanaMboxes.MBOX1.MSGID.all = 0x00040000; // Std identifier
ECanaMboxes.MBOX2.MSGID.all = 0x00080000; // Std identifier
ECanaMboxes.MBOX3.MSGID.all = 0x000C0000; // Std identifier
ECanaMboxes.MBOX4.MSGID.all = 0x00100000; // Std identifier
ECanaMboxes.MBOX5.MSGID.all = 0x00140000; // Std identifier
ECanaMboxes.MBOX6.MSGID.all = 0x00180000; // Std identifier
ECanaMboxes.MBOX7.MSGID.all = 0x001C0000; // Std identifier
ECanaMboxes.MBOX8.MSGID.all = 0x00200000; // Std identifier
ECanaMboxes.MBOX9.MSGID.all = 0x00240000; // Std identifier
ECanaMboxes.MBOX10.MSGID.all = 0x00400000; // Std identifier
ECanaMboxes.MBOX11.MSGID.all = 0x00440000; // Std identifier
ECanaMboxes.MBOX12.MSGID.all = 0x00480000; // Std identifier
ECanaMboxes.MBOX13.MSGID.all = 0x004C0000; // Std identifier
ECanaMboxes.MBOX14.MSGID.all = 0x00500000; // Std identifier
ECanaMboxes.MBOX15.MSGID.all = 0x00540000; // Std identifier
ECanaMboxes.MBOX16.MSGID.all = 0x00580000; // Std identifier
ECanaMboxes.MBOX17.MSGID.all = 0x005C0000; // Std identifier
ECanaMboxes.MBOX18.MSGID.all = 0x00600000; // Std identifier
ECanaMboxes.MBOX19.MSGID.all = 0x00640000; // Std identifier
ECanaMboxes.MBOX20.MSGID.all = 0x00800000; // Std identifier
ECanaMboxes.MBOX21.MSGID.all = 0x00840000; // Std identifier
ECanaMboxes.MBOX22.MSGID.all = 0x00880000; // Std identifier
ECanaMboxes.MBOX23.MSGID.all = 0x008C0000; // Std identifier
ECanaMboxes.MBOX24.MSGID.all = 0x00900000; // Std identifier
ECanaMboxes.MBOX25.MSGID.all = 0x00940000; // Std identifier
ECanaMboxes.MBOX26.MSGID.all = 0x00980000; // Std identifier
ECanaMboxes.MBOX27.MSGID.all = 0x009C0000; // Std identifier
ECanaMboxes.MBOX28.MSGID.all = 0x00A00000; // Std identifier
ECanaMboxes.MBOX29.MSGID.all = 0x00A40000; // Std identifier
ECanaMboxes.MBOX30.MSGID.all = 0x00C00000; // Std identifier
ECanaMboxes.MBOX31.MSGID.all = 0x00C40000; // Std identifier
ECanaMboxes.MBOX0.MSGID.all = 0x00C80000; // Std identifier
ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;
ECanaShadow.CANMD.all = 0xFFFFFFFF;
ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;
/* Enable Mailboxes */
ECanaShadow.CANME.all = ECanaRegs.CANME.all;
ECanaShadow.CANME.all = 0xFFFFFFFF;
ECanaRegs.CANME.all = ECanaShadow.CANME.all;
/* Begin receiving */
while(1)
{
while(ECanaRegs.CANRMP.all != 0x00000020 ) {} // Wait for all RMPn to be set..
ECanaRegs.CANRMP.all = 0x00000020; // Clear all RMPn bits and start
RXCOUNT++ ;
for(j=1; j<32; j++) // Read & check 16 mailboxes
{
mailbox_read(j); // This func reads the indicated mailbox data
mailbox_check(TestMbox1,TestMbox2,TestMbox3); // Checks the received data
} // all over again...
}
}
void mailbox_read(int16 MBXnbr)
{
volatile struct MBOX *Mailbox;
Mailbox = &ECanaMboxes.MBOX0 + MBXnbr;
TestMbox1 = Mailbox->MDL.all;
TestMbox2 = Mailbox->MDH.all;
TestMbox3 = Mailbox->MSGID.all;
void mailbox_check(int32 T1, int32 T2, int32 T3)
{
if((T1 != T3) || ( T2 != 0x89ABCDEF))
{
ErrorCount++;
}
else
{
PassCount++;
}
}
------------------------------------------------------------------------------------------------------------------------------------------
The RXCOUNT is getting incremented when the while loop shown above is commented ; but CANRMP is always 0x00000000.
Pls help!
Keerthi