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CCE bit in CAN controller of F2812 is not set, hence program control is not moving ahead.

SUNIL SAWANT
Intellectual 955 points

Other Parts Discussed in Thread: TMS320F2812, CCSTUDIO

I am working on using CAN interface of F2812 dsp controller. I have used sample code available on TI website. However, sample code is not working. CCE bit in CANES register is not set. Processor is waiting for CCE bit to set and hence program control is not moving ahead (Code mentioned in bold). Could anybody suggest a solution to the problem ?

Program is here:

void InitECan(void)
{
 long i = 0;
 
 asm(" EALLOW");
 
/* Disable Watchdog  */
   
    SysCtrlRegs.WDCR = 0x006F;
   
/* Enable clock to CAN module  */  
   
    SysCtrlRegs.PCLKCR.all = 0x4000;
   
/* Set PLL multiplication factor */
   
//    SysCtrlRegs.PLLCR.bit.DIV = 0x000A;  // Set PLL to x10 (/2). A CLKIN of 30 MHz would result in
              // 30 * 10 = 300 (/2) = 150 MHz SYSCLKOUT.

    SysCtrlRegs.PLLCR = 0x000A;    // Set PLL to x10 (/2). A CLKIN of 30 MHz would result in
              // 30 * 10 = 300 (/2) = 150 MHz SYSCLKOUT.
    
    for(i = 0; i < 100000; i++)    // Delay for PLL to stabilize
   {asm("NOP");}
 
/* Configure eCAN pins using GPIO regs*/
 
 GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
 GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
 
/* Configure eCAN RX and TX pins for eCAN transmissions using eCAN regs*/ 
   
    ECanaRegs.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANRIOC.bit.RXFUNC = 1;
 
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
           // HECC mode also enables time-stamping feature
// ECanaRegs.CANMC.bit.SCB = 1;
 ECanaRegs.CANMC.bit.SCM = 1;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MCF register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MCF must be initialized to zero
  
    ECanaMboxes.MBOX0.MCF.all = 0x00000000;
    ECanaMboxes.MBOX1.MCF.all = 0x00000000;
    ECanaMboxes.MBOX2.MCF.all = 0x00000000;
    ECanaMboxes.MBOX3.MCF.all = 0x00000000;
    ECanaMboxes.MBOX4.MCF.all = 0x00000000;
    ECanaMboxes.MBOX5.MCF.all = 0x00000000;
    ECanaMboxes.MBOX6.MCF.all = 0x00000000;
    ECanaMboxes.MBOX7.MCF.all = 0x00000000;
    ECanaMboxes.MBOX8.MCF.all = 0x00000000;
    ECanaMboxes.MBOX9.MCF.all = 0x00000000;
    ECanaMboxes.MBOX10.MCF.all = 0x00000000;
    ECanaMboxes.MBOX11.MCF.all = 0x00000000;
    ECanaMboxes.MBOX12.MCF.all = 0x00000000;
    ECanaMboxes.MBOX13.MCF.all = 0x00000000;
    ECanaMboxes.MBOX14.MCF.all = 0x00000000;
    ECanaMboxes.MBOX15.MCF.all = 0x00000000;
    ECanaMboxes.MBOX16.MCF.all = 0x00000000;
    ECanaMboxes.MBOX17.MCF.all = 0x00000000;
    ECanaMboxes.MBOX18.MCF.all = 0x00000000;
    ECanaMboxes.MBOX19.MCF.all = 0x00000000;
    ECanaMboxes.MBOX20.MCF.all = 0x00000000;
    ECanaMboxes.MBOX21.MCF.all = 0x00000000;
    ECanaMboxes.MBOX22.MCF.all = 0x00000000;
    ECanaMboxes.MBOX23.MCF.all = 0x00000000;
    ECanaMboxes.MBOX24.MCF.all = 0x00000000;
    ECanaMboxes.MBOX25.MCF.all = 0x00000000;
    ECanaMboxes.MBOX26.MCF.all = 0x00000000;
    ECanaMboxes.MBOX27.MCF.all = 0x00000000;
    ECanaMboxes.MBOX28.MCF.all = 0x00000000;
    ECanaMboxes.MBOX29.MCF.all = 0x00000000;
    ECanaMboxes.MBOX30.MCF.all = 0x00000000;
    ECanaMboxes.MBOX31.MCF.all = 0x00000000;
 
// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.
 
/* Clear all TAn bits */
 
 ECanaRegs.CANTA.all = 0xFFFFFFFF;
 
/* Clear all RMPn bits */
 
 ECanaRegs.CANRMP.all = 0xFFFFFFFF;
 
/* Clear all interrupt flag bits */  
 
 ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
 ECanaRegs.CANGIF1.all = 0xFFFFFFFF;
 
/* Configure bit timing parameters */
 
 ECanaRegs.CANMC.bit.CCR = 1 ;             // Set CCR = 1
    
 -->   while(ECanaRegs.CANES.bit.CCE != 1) {}    // Wait for CCE bit to be set..  <--
    
    ECanaRegs.CANBTC.bit.BRP = 9;
    ECanaRegs.CANBTC.bit.TSEG2 = 2;
    ECanaRegs.CANBTC.bit.TSEG1 = 10;
   
    ECanaRegs.CANMC.bit.CCR = 0 ;              // Set CCR = 0
    while(ECanaRegs.CANES.bit.CCE == !0) {}    // Wait for CCE bit to be cleared..
 
/* Disable all Mailboxes  */
 
  ECanaRegs.CANME.all = 0;     // Required before writing the MSGIDs
 
 asm(" EDIS");         // Disable EALLOW protected register access
}

  • 0
    Mastermind 7585 points

    Syntax error. Check your code:  PLLCR is a union. The correct line should be SysCtrlRegs.PLLCR.all = 0x000A;    

     

  • 0 in reply to Frank Bormann
    Intellectual 955 points

    Hello Frank,

    I tried incorporating the changes you suggested. But compiler is showing errors. Please check below for error log.

     

    ---------------------  TMS320F2812_CAN_Driver.pjt - Debug  ---------------------
    [TMS320F2812_InitECAN.c] "C:\CCStudio_v3.3\C2000\cgtools\bin\cl2000" -g -fr"D:/Projects/CBPro/Software/Embedded/TMS320F2812 CAN Driver/Debug" -d"_DEBUG" -d"LARGE_MODEL" -ml -v28 -@"Debug.lkf" "TMS320F2812_InitECAN.c"
    "TMS320F2812_InitECAN.c", line 61: error: expression must have struct or union type
    1 error detected in the compilation of "TMS320F2812_InitECAN.c".

    >> Compilation failure

    Build Complete,
      1 Errors, 0 Warnings, 0 Remarks.

     

    Moreover, as suggested PLLCR is not a structure. It is an element of a structure in DSP28_SysCtrl.h file as mentioned below.

    struct SYS_CTRL_REGS {
       Uint16  rsvd1[10];            // 0-9
       union HISPCP_REG HISPCP;      // 10: High-speed peripheral clock pre-scaler
       union LOSPCP_REG LOSPCP;      // 11: Low-speed peripheral clock pre-scaler
       union PCLKCR_REG PCLKCR;      // 12: Peripheral clock control register
       Uint16  rsvd2;                // 13
       Uint16  LPMCR0;               // 14: Low-power mode control register 0
       Uint16  LPMCR1;               // 15: Low-power mode control register 1
       Uint16  rsvd3;                // 16
       Uint16  PLLCR;                // 17: PLL control register
       union SCSR_REG SCSR;          // 18: System control and status register
       Uint16  WDCNTR;               // 19: WD counter register
       Uint16  rsvd4;                // 20
       Uint16  WDKEY;                // 21: WD reset key register
       Uint16  rsvd5[3];             // 22-24
       Uint16  WDCR;                 // 25: WD timer control register
       Uint16  rsvd6[6];             // 26-31
    };

    Problem not solved.

     

  • 0 in reply to SUNIL SAWANT
    TI__Mastermind 22025 points

    Sunil,

    You've clearly been messing with the header files....

    In your code you have commented out:

    //    SysCtrlRegs.PLLCR.bit.DIV = 0x000A;  // Set PLL to x10 (/2). A CLKIN of 30 MHz would result in
                  // 30 * 10 = 300 (/2) = 150 MHz SYSCLKOUT.

    which clearly shows that at some point the PLLCR register was a union of a bits structure and a full blow uint16_t.  Then you actually set:

        SysCtrlRegs.PLLCR = 0x000A;    // Set PLL to x10 (/2). A CLKIN of 30 MHz would result in
                  // 30 * 10 = 300 (/2) = 150 MHz SYSCLKOUT.

    which says that PLLCR is no longer a structure, but in the header files we distribute you'll see:

    //---------------------------------------------------------------------------
    // System Control Register File:
    //
    struct SYS_CTRL_REGS {
       Uint16  rsvd1[10];            // 0-9
       union   HISPCP_REG HISPCP;    // 10: High-speed peripheral clock pre-scaler
       union   LOSPCP_REG LOSPCP;    // 11: Low-speed peripheral clock pre-scaler
       union   PCLKCR_REG PCLKCR;    // 12: Peripheral clock control register
       Uint16             rsvd2;     // 13: reserved
       union   LPMCR0_REG LPMCR0;    // 14: Low-power mode control register 0
       union   LPMCR1_REG LPMCR1;    // 15: Low-power mode control register 1
       Uint16             rsvd3;     // 16: reserved
       union   PLLCR_REG  PLLCR;     // 17: PLL control register
       // No bit definitions are defined for SCSR because
       // a read-modify-write instruction can clear the WDOVERRIDE bit
       Uint16             SCSR;      // 18: System control and status register
       Uint16             WDCNTR;    // 19: WD counter register
       Uint16             rsvd4;     // 20
       Uint16             WDKEY;     // 21: WD reset key register
       Uint16             rsvd5[3];  // 22-24
       // No bit definitions are defined for WDCR because
       // the proper value must be written to the WDCHK field
       // whenever writing to this register.
       Uint16             WDCR;      // 25: WD timer control register
       Uint16             rsvd6[6];  // 26-31
    };

    So thats why you're getting that error when you follow Frank's suggestions. 

    Quick question, are you the one having trouble getting the CCE bit set when running from flash? but then it works when running from RAM?

    Regards,

    Trey