Hi all,
I am struggling to configure concerto UART0 in FIFO mode. I would have an Rx interrupt if the receive buffer has 4 bytes received (1/4 of the buffer full) and would on the other hand only send my messages if the Tx buffer is 1/4 full.
until now, i get always an interrupt regardless what I define in the FIFO settings.
Here is my intialization code:
extern "C"
{
void primComm_Handler()
{
if (0!=PrimCommDriver::pPrimCommDriver)
PrimCommDriver::pPrimCommDriver->rxInterrupt();
}
}
PrimCommDriver::PrimCommDriver()
{
pPrimCommDriver = this;
UARTDisable(UART0_BASE);
UARTConfigSetExpClk(UART0_BASE, ulUARTClk, ulBaud, ulConfig);
UARTFIFOLevelSet(UART0_BASE, UART_FIFO_TX2_8, UART_FIFO_RX2_8);
UARTFIFOEnable(UART0_BASE);
IntRegister(INT_UART0, primComm_Handler);
IntEnable(INT_UART0);
UARTTxIntModeSet(UART0_BASE, UART_TXINT_MODE_FIFO);
UARTIntEnable(UART0_BASE, UART_INT_RX | UART_INT_RT);
UARTEnable(UART0_BASE);
}
void PrimCommDriver::rxInterrupt(void)
{
/*Here I put a breakpoint and observe the register values. */
}
In my breakpoint I never see, that the FIFO Rx Buffer becomes full. What am I missing?? Where hides the bug??
BR Andreas
