On my 28346 application, I have 2 external interrupts coming fairly fast -- each one every 25us and offset from each other at ~12us. I have them connected to the INT1 group, so they should be the highest priority interrupts in the system. The ISR themselves execute in 6-8us, so I should the bandwidth to do this. At the end of each ISR, I ACK the group 1 PIE (PieCtrlRegs.PIEACK.all = PIEACK_GROUP1), however occasionally both interrupts stop because the group is not ACKed.
I tried setting PIEACK as the first line in each ISR and at the last line, with no change (I did not think it would affect the result).
Also there are no other active interrupts in this group (no Timer0 nor WAKEINT).
1) Does it matter if the PIEACK occurs at the beginning or end of the ISR? If so, why?
2) Is there a problem with my method of alternating external interrupts in the same group?
3) It is possible (although not confirmed) that these external interrupts (the GPIO signals themselves) overlap, but that should not be a problem, right?
Thanks,
Jim