Other Parts Discussed in Thread: TMS320F28030
Hello,
Can you please help clarify the min/max frequencies on the PLL VCOCLK that can be used in the TMS320F28030 parts? The only reference to this specification I could find in the datasheet is a note in Sec. 3.8.3 stating:
"The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of
the PLL (VCOCLK) is at least 50 MHz."
Sec. 6.7, 6.8 do not include a min/max specification for VCOCLK.
Can I infer that the VCOCLK minimum is 50MHz, and the maximum is max(SYSCLKOUT)*4 = 240MHz?
Any help is appreciated, thank you,
Colin