Welcome
The task is to generate multiple sinusoidal signals with different frequencies.
The first DMA channel is working properly, but not the second.
May be there is some mistake, please help to find it.
EALLOW;
PieVectTable.DINTCH1 = &dma_isr;
EDIS;
DINT;
// clear any pending interrupt for DMA
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; //INT7.1 is DMA_CH1_INT
IER |= M_INT7; // Enable CPU Interrupt 7
EINT; // Enable Global interrupt INTM
EALLOW;
// Enable DMA clock
SysCtrlRegs.PCLKCR3.bit.DMAENCLK = 1;
// Reset the DMA (also sets round-robin priority scheme)
DmaRegs.DMACTRL.bit.HARDRESET = 1;
asm(" NOP");
// DMA channel 1:
// triggered by ePWM1 SOCA
// writes one 16-bit word to ePWM1 CMPA
//DmaRegs.CH1.CONTROL.bit.SOFTRESET = 1;
DmaRegs.CH1.MODE.bit.CHINTE = 1; // want to get interrupts to CPU
DmaRegs.CH1.MODE.bit.CHINTMODE = 0; // at the beginning of each transfer
DmaRegs.CH1.MODE.bit.DATASIZE = 0; // 16-bit words
DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // no need to restart
DmaRegs.CH1.MODE.bit.ONESHOT = 0; // 1 burst per event
DmaRegs.CH1.MODE.bit.PERINTSEL = 18; // ePWM1 SOCA triggers this channel
DmaRegs.CH1.MODE.bit.PERINTE = 1; // enable peripheral interrupt
DmaRegs.CH1.BURST_SIZE.bit.BURSTSIZE = SAMPLE_SIZE - 1; // 0 is one word in a burst
DmaRegs.CH1.TRANSFER_SIZE = active_context->samples - 1; // bursts in a transfer
DmaRegs.CH1.SRC_BURST_STEP = 1; // go to next word in sample
DmaRegs.CH1.SRC_TRANSFER_STEP = 1; // go to next sample
DmaRegs.CH1.SRC_WRAP_SIZE = active_context->samples - 1;
DmaRegs.CH1.SRC_WRAP_STEP = 0; // BEG_ADDR remains unchanged
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)(&(active_context->buffer[0]));
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)(&(active_context->buffer[0]));
DmaRegs.CH1.DST_BURST_STEP = SAMPLE_SIZE - 1;
DmaRegs.CH1.DST_TRANSFER_STEP = -(SAMPLE_SIZE - 1);
// wrap disabled (>TRANSFER_SIZE)
DmaRegs.CH1.DST_WRAP_SIZE = BUF_SAMPLES;
DmaRegs.CH1.DST_WRAP_STEP = 0;
if(USE_HIRES)
{
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)(&(EPwm1Regs.CMPA));
}
else
{
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)(&(EPwm1Regs.CMPA.half.CMPA));
}
// Start CH1
DmaRegs.CH1.CONTROL.bit.RUN = 1;
// DMA channel 2:
// triggered by ePWM2 SOCA
// writes one 16-bit word to ePWM1 CMPA
//DmaRegs.CH2.CONTROL.bit.SOFTRESET = 1;
DmaRegs.CH2.MODE.bit.CHINTE = 0; // want to get interrupts to CPU
DmaRegs.CH2.MODE.bit.CHINTMODE = 0; // at the beginning of each transfer
DmaRegs.CH2.MODE.bit.DATASIZE = 0; // 16-bit words
DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // no need to restart
DmaRegs.CH2.MODE.bit.ONESHOT = 0; // 1 burst per event
DmaRegs.CH2.MODE.bit.PERINTSEL = 20; // ePWM2 SOCA triggers this channel
DmaRegs.CH2.MODE.bit.PERINTE = 1; // enable peripheral interrupt
DmaRegs.CH2.BURST_SIZE.bit.BURSTSIZE = SAMPLE_SIZE - 1; // 0 is one word in a burst
DmaRegs.CH2.TRANSFER_SIZE = active_context2->samples - 1; // bursts in a transfer
DmaRegs.CH2.SRC_BURST_STEP = 1; // go to next word in sample
DmaRegs.CH2.SRC_TRANSFER_STEP = 1; // go to next sample
DmaRegs.CH2.SRC_WRAP_SIZE = active_context2->samples - 1;
DmaRegs.CH2.SRC_WRAP_STEP = 0; // BEG_ADDR remains unchanged
DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)(&(active_context2->buffer[0]));
DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)(&(active_context2->buffer[0]));
DmaRegs.CH2.DST_BURST_STEP = SAMPLE_SIZE - 1;
DmaRegs.CH2.DST_TRANSFER_STEP = -(SAMPLE_SIZE - 1);
// wrap disabled (>TRANSFER_SIZE)
DmaRegs.CH2.DST_WRAP_SIZE = BUF_SAMPLES;
DmaRegs.CH2.DST_WRAP_STEP = 0;
if(USE_HIRES)
{
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)(&(EPwm2Regs.CMPA));
}
else
{
DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)(&(EPwm2Regs.CMPA.half.CMPA));
}
// Start CH2
DmaRegs.CH2.CONTROL.bit.RUN = 1;
EDIS;
}
Best regards, Vitaliy
