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Pull down resistor

viju nair
Intellectual 305 points
Other Parts Discussed in Thread: TMS320F2812

Sir

In my PCB( solar inverter) ,i have a pin which is pulled down thru 2.2k resistor ,as such this pin is clean wrt the ground of PCB.

But the moment i connect this pin to the ENABLE pin of buffer IC(74hct540),it picks up the switching noise(other input pins of buffer are receiving PWM signals from DSP) whose magnitude increases with the DC link voltage .

The same thing happens if i connect this to a GPIO pin of DSP(TMS320F2812).Actually i need to connect above pin to both of them.(for protection purpose)

The noise occurs during the rise time of PWM signals

I don't think there is anything wrong with PCB as it was made by an expert(still iam not ruling it out......)

I can provide u with schematic of my board if needed.....

plz reply

thanking u

Viju Nair.R

  • 0
    TI__Guru 57255 points

    Viju,

    Can you quantify the magnitude of noise that you are seeing?  Is the noise flipping the IO logic from 0 to 1 or is the noise just an inconvenience?  Is there a particular reason that this particular IO must be absolutely clean?

    In nearly all systems, some noise will be introduced in signals.  The key to minimizing noise is good layout and proper decoupling. 


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Intellectual 305 points

    As u said,its flipping the logic from 0 to1 and the noise level increases with increase in my DC link voltage

    its width is very small,but magnitude can reach upto 2V(i hv not increased my dc link further,may b noise level can go even higher)

    Whenever a high is detected on ENABLE pin (active low))of buffer IC,it should disable the PWM signals reaching the power switches,Also a high on the GPIO pin should trigger an external interrupt and force high all PWM signals(buffer is an inverting one) .The high indicates that an overcurrent has occurred.

    In my case even when current is far below the limits,its tripping inadvertently bcoz of this noise.

    thank u for ur reply

    plz respond

    thanking u

    viju nair

    IIT Bombay

  • 0 in reply to viju nair
    TI__Guru 57255 points

    A schematic (or a partial schematic), may be useful to debug.

    A few questions:
    1) It seems you have a GPIO pin connected to the enable pin of the buffer IC.  How is this IO pin configured?  As a GPIO input (Hi-Z) or is it a GPIO output and driving the IO low?   How is the IO (that is used for protection purposes) configured?
    2) Could you try to add ~100nF of capacitance between the IO net trace that is switching and ground.


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Intellectual 305 points

    I can send u complete orcad schematic  to ur personal email id if u can provide .(since this project is related to highly funded research work at IIT Bombay)

    Yes,GPIO pin is connected to enable pin of buffer IC

    Any rising edge on this GPIO pin will trigger an external interrupt(XINT1) and force high all PWMs.

    GPIO pin is configured as an input pin but otherwise also without connecting to GPIO pin,if i connect directly to the enable pin ,it shows same switching noise.

    100nF is slightly higher ,Already 100pF is connected at all PWM signal outputs and 0.1nF is connected at the point connected to the GPIO pin wrt ground of PCB.

    Increasing beyond 0.1nF,will further delay the high signal detected on the GPIO pin as well as enable pin of buffer IC.


    thanking u

    viju nair