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[Concerto] C28 Boot from RAM

Carlos Sanza
Prodigy 100 points

I am trying to boot Concerto Control Subsystem from RAM , for debbuging purposes, waking up the C28 from IDLE using this IPC function in the M3 code:

IPCMtoCBootControlSystem(CBROM_MTOC_BOOTMODE_BOOT_FROM_RAM);

One issue I have found (according to 6.6.2: C-Boot ROM RAM Initialization from the TRM SPRUH22B) is that C-Boot ROM zero-initializes the M0 RAM every time it is RUN after the control subsystem reset.

I can not find a way to get the C28 waiting at idle without a previous reset, so when the M3 tries to wake the C28 up with the IPC Boot function, the M0 RAM memory (where "code_start" lies at address 0x000000), has already been initialized. Then, instead of jumping to _c_int00 and later to main, it results into an iTRAP exception.

Meanwhile, one alternative option I've tried (from the TI wiki http://processors.wiki.ti.com/index.php/Concerto_Dual_Core_Boot ) is commenting the IPC Boot function at M3 code and just load and run both cores manually, using standard GEL file and without having C28 waiting at IDLE.

Thanks in advance

  • 0
    TI__Mastermind 19810 points

    Carlos,

    I guess you are trying to load code on C28x from debugger (CCS) and then you are doing a debug reset and re-starting the C-boot ROM. In this case yes, M0 RAM will be Zero Initialized. This is being fixed in the next version of the device in the concerto family.

    Meanwhile to continue your debug, you could use the method you suggested above (from the twiki page) or link and load your code to a memory other than M0 RAM and use IPC branch call to have C-Boot ROM branch to the application start.

    Hope it helps.

    Best Regards

    Santosh

  • 0 in reply to Santosh Athuru
    Prodigy 100 points

    Thank you very much Santosh