I am currently prototyping on a TMX320F28045PN (part of a ControlCard) and just came across the errata for the Rev 0 silicon I'm using. Of the features I'm using, I should expect to see based on http://focus.ti.com/lit/er/sprz295b/sprz295b.pdf:
1) Issues with the first ADC conversion in a sequence. My implementation currently monitors 6 ADC channels in 2 different conversion sequences and hasn't run into any conversion issues yet. Possibly just lucky, will be investigating that further.
2) Prefetching past valid memory at the end of M1 causing indeterminte states. Also, likely I've just gotten lucky there.
3) CSM locking activated by reads of 0x3D7FF8 through 0x3D7FFF. Now, since the prefetching erratat from section 2 will prefetch past the end of Flash A (last section of Flash memory, directly preceeds CSM locations), I would expect to see an issue from the branch instruction in my BEGIN section (chunk of linker cmd file below).
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL_P0 : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
I haven't seen any mysterious locking so far, so are prefetches not reads as far as CSM is concerned? Or is it possible that the prefetch isn't occuring?
Please let me know if there is any additional information I can provide.
Regards,
Louis