ADC accuracy of different 28x DSPs?

Stephan,

You can achieve pretty good accuracy with the ADCs on the F28xx devices by using appropriate layout recommendations and also using calibration. The F280xx, F2833x, and F2802x ADCs also contain Offset Trim registers to reduce the inherent offset. You can read more about the offset trim in each of these devices ADC Manuals. We have a couple of app notes to show the calibration scheme. You can download these at the following links:

http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=spraad8a

http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=spra989a

To get recommendations for proper layout you can follow our Hardware Design Guidelines and Overview for Designing Analog Interface Application Notes. These documents are available at the following links:

http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=spraap6a

http://focus.ti.com/general/docs/techdocsabstract.tsp?abstractName=spraas1a

Regards,

Tim Love

Tim,

Thanks for your hints and the links to the app notes.

We already knew these app notes and followed them in our layout and software, but the 2812 ADC was still bad.

The problem is that the hints in the app notes mainly reduce the static ADC error, but not the noise. It reduced the 12 bit ADC on the 2812 to effective 9..10 bit.

So I would like to get some input for the 280x ADC regarding noise compared to the 2812. According to the datasheet, the static error seems to be better on the newer devices.

Stephan,

You are correct that the effective bits for the 2812 is around 10. It is specified as typical 10.1 bits. With the 2808 inherent errors and noise were improved and you are looking at about 10.9 effective bits. The gain error was improved from +/- 5 % to +/- 1.5%.

Regards,

Tim Love

I picked this conversation from the forum because I am disturbed by datasheet of TMS320F28035 error values for gain and offset being +/- 60 and +/- 20 LSB. Is that really not too high ? There is no mention of "effective bits" in there.

The gain error is deceiving; this is worst case guaranteed error over the full temperature range of the "S"(-40C  - 125C) device.  The gain of this ADC is derived from an internal band gap Vref with a temperature coeff of ~80ppm/degC.  Internal reference is necessary to give fixed range conversion from 0-3.3V regardless of VDDA level.  This is the same specification as the F280x class of ADCs for this parameter.  At nominal temperatures the gain error should be much lower at the mid point temperature of the device spec. 

The offset error can be fully compensated using the OFFTRIM register in the ADC.  The 28035 device supports an internal connection to sample VREFLO signal and then loading the corresponding correction value into the OFFTRIM register to compensate.  This is detailed in the ADC UG.  It is worth noting this correction is in the analog domain, so native voltage range is preserved.

I believe I understand what you mean by effective bits in this context; but traditionally ENOB is reserved for SNR/SINAD AC characteristics which is not 1:1 related to accuracy(which is your concern).  This accuracy/DC "ENOB" can be called total error of the ADC, which is cumulative of gain, offset, and INL errors.

Best,

Matthew

Matthew,

Thanks.

What do you mean by "At nominal temperatures the gain error should be much lower at the mid point temperature of the device spec." You are talking about two temperatures here. Can you give an example of the gain error ? How does the gain error get affected by calibration. DOes it improve or the gain specified is assuming a calibration.

Will the offset error almost be 0 if calibration is done ? May be I have to read your app notes to understand the process of calibration before I raise more questions.

You have brought up a new term "total error" that I have come across in NXP datasheet ('absolute error ?')but I have not seen it in TI datasheet. Can you tell me the numerical value of the "total error" for TMS320F28035 ?

sunil

I added that comment at the last minute, and it bit me :)  What I'm trying to say is that at 30C, for example, the gain error will probably be within +/-10LSBs.  Max gain error should only be seen at the temperature corners.

Furthermore, gain error is a scaling error dependent on the voltage being converted.  Spec of 60LSB error is only at rail input of 3.3V; mid scale input of 1.65V gain error would be 30LSBs.  It is easier to consider this error as a percentage, i.e. 1.46%.  Translating to the above, 30C, it would be  0.244% error of the input voltage.

Offset is a constant adder, so could be 20LSBs at any voltage.  You are correct that offset can be almost 0 post calibration. 

This is the same term, worst case I could describe absolute/total error as the sum of the errors I mentioned, in this case 20LSBs+60LSBs+2LSBs, or 82LSBs native.  Considering what I have described you can see this is pessimistic, since gain error is a scaling error, and offset can be corrected.

I'm not sure the NXP device in question, but one thing to consider is if it has internal reference or not.  If ADC has pure external reference, then ADC is passing accuracy requirement to you/BOM to maintain some tolerance over temperature.

For the sake of the forum we are working to improve the temperature coefficient of the reference(which would help the total gain error spec).

Best,

Matthew

Matthew,

Last question before I begin my weekend. Can I improve gain error by calibration and how much ?

sunil

Sunil,

This is dependent on the ch/ch errors for the ADC, I need to check with the correct folks and get back to you on this.  I can say this is usually in the +/-4LSB range for our other devices, I'm not expecting much of a surprise on this device either, but will confirm on Monday.

Only other consideration is that you would have to sacrifice a channel for this calibration for the reference.

Best,

Matthew