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SW RESET Timing

A Break Detect (reg SCIRXST bit BRKDT) has occurred on the SCI Receive using a TMS320x28 micro.  I read that to allow the receive data interrupt to be generated for following receive characters I must issue a SW RESET.  What I plan to do is clear the SW RESET bit and then set it back to a 1.  What I would like to know is do I need to put NOP's between the two instructions and if so, how many?