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Concerto C28 flash issue

Jeff Talbott
Intellectual 470 points


I notice an issue when returning to a ramfunc from a flash func.  The stack pointer is not correct.  In this case it is 2 less than it should be.  The stack points to a value 0x0000 which eventually results in Illegal_ISR() call.

I am running bootloader.  The code jumps to run-time program.  Everything is fine until a specific function is called.  The caller is located in RAM.  The destination function is located in flash.  If i step over the function call in RAM, the stack pointer is less than it should be.  This is the dissassembly for the flash function:

FE08        ADDB         SP, #8

7D45        MOV          *-SP[5], AR5

1E44        MOVL         *-SP[4], ACC

7C41        MOV          *-SP[1], AR4

28AC000E    MOV          @T, #0x000e

8F0128E6    MOVL         XAR4, #0x0128e6

E2880044    I32TOF32     R0H, *-SP[4]

3041        MPYXU        ACC, T, *-SP[1]

560100A4    ADDL         @XAR4, ACC

E2AF01C4    MOV32        R1H, *+XAR4[0], UNCF

E7000008    MPYF32       R0H, R1H, R0H

7700        NOP         

E2030048    MOV32        *-SP[8], R0H

9245        MOV          AL, *-SP[5]

EC0D        SBF          C$L1, EQ

3041        MPYXU        ACC, T, *-SP[1]

8F0128E8    MOVL         XAR4, #0x0128e8

560100A4    ADDL         @XAR4, ACC

E2AF01C4    MOV32        R1H, *+XAR4[0], UNCF

E7100008    ADDF32       R0H, R1H, R0H

7700        NOP        

E2030048    MOV32        *-SP[8], R0H

FE88        SUBB         SP, #8

0006        LRETR     

 

More details about this: C28 RWAIT = 3, C28x clock is 150MHz, M3 is 75MHz, ECC is disabled, Prefetch is enabled. 

If I changed the flash wait state to RWAIT = 8, the code seems to execute normally.  However RWAIT < 8 does not.

If I add a few lines of code causing the placement of the flash function to change (even just by 6 address locations), the symptons go away.  I wonder if the issue is just masked in this case?

 

Also, i saw a note in the silicon errata regarding SBF and the flash prefetch causing an issue.  I used the -me option, and the problem seems to go away.  However, i am not convinced that all issues have been solved.  Has it just moved to a different location?

 

Any ideas?  I am concerned i have this issue in other function calls, but maybe the stack pointer just happens to be correct although the data used may not be.

  • 0
    TI__Guru* 87155 points

    Jeff,

    I see that you confirm that the issue is not there when you use -me option with any waitstate. 

    Your observation is correct;  Compiler will avoid SBF/BF instructions if you use -me option and hence you should not have issue at any other part of the code.

    If you are still concerned, looks like you can use the disasembler tool to check if there are any other SBF/BF instructions in your object files.  If you have any data tables embedded in your code (for example arrays or constants), please note that disasembler would show them out too as some opcodes and you might see some SBF/BF instructions as well for this reason.  You can see the memory locations where these data tables are allocated and ruleout the corresponding SBF/BF instructions (if any) pointed by the disasembler to avoid confusion.

    You can get details on disassembler tool in TMS320C28x Assembly Language Tools users guide.  This should be available in your CCS installation directory.  For CCS5, this is available at ccsv5\tools\compiler\c2000_6.1.0\docs folder.

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Intellectual 470 points

    Ok.  So I used the dis2000 to confirm the SBF and BF instructions are not used in my code.  However, they are used throughout the rts2800_fpu32.lib.  I guess this would be ok if they were executed from RAM, but they are not.  Even args_main() uses the SBF instruction.  This would mean c_int00 would have to be modified.

     

    Is this an issue?

     

  • 0 in reply to Jeff Talbott
    TI__Guru* 87155 points

    Jeff,

    RTS library source files are provided at ccsv5\tools\compiler\c2000_6.1.0\lib.  Source can be modified and recompiled with -me option to avoid SBF/BF instructions.

    Thanks and regards,

    Vamsi

     

  • 0 in reply to Vamsi Gudivada
    Intellectual 470 points

    Well i rebuilt the rts2800_fpu library to disable the fast branch instructions.  It looks liked it worked.  Now i realize the FAPI lib uses them as well.

     

    Is rebuilding every library really the best way to handle this?  The example projects in control suite enable the prefetch.  How do they get around the fast branch issue?

  • 0 in reply to Jeff Talbott
    TI__Guru* 87155 points

    Jeff,

    Flash API library functions are supposed to be executed from RAM in Concerto.  So, it is ok to have SBF/BF instructions in Flash API.

    Unfortunately, any library functions that you are executing from Flash should not have SBF/BF and hence need to be recompiled.  We understand the pain and please note that we are fixing this bug in our next silicon revision.

    Example projects in control suite will be updated to compile with -me option for now.

    Thanks and regards,

    Vamsi

  • 0 in reply to Vamsi Gudivada
    Intellectual 470 points

    Thanks for your help.

  • 0 in reply to Jeff Talbott
    Intellectual 470 points

    If prefetch and data cache are disabled, should I be able to run the fast branch instructions from flash?

  • 0 in reply to Jeff Talbott
    TI__Guru* 87155 points

    Jeff,

    Yes, with prefetch disabled, you should be able to execute SBF/BF from Flash.

    Thanks and regards,
    Vamsi

  • 0 in reply to Vamsi Gudivada
    Intellectual 470 points

    Has the flash clock frequency been determined for the concerto?

    This is what the data sheet says:

     

    NOTE:

    Flash characterization is pending for F28M35x devices; therefore the allowed maximum flash

    clock frequency with one wait state (FCLK max) is not given in the device data manual.

    However from design simulations, FCLK max can be given as 40MHz. This value will be

    updated later in the data manual when Flash characterization is complete.

  • 0 in reply to Jeff Talbott
    TI__Guru* 87155 points

    Jeff,

    Characterization is on going and we can expect the results in 5 to 6 weeks.  We will update the datasheet at that time.

    Thanks and regards,
    Vamsi