Other Parts Discussed in Thread: TMDSDOCK28335, TMDSCNCD28335, TMS320F28335
The Rev 1.1 TMDSCNCD28335 controlCARD that comes with the TMDSDOCK28335 Experimenter's Kit has a 20MHz crystal connected to the f28335 processor.
Referring to Table 3-16. PLL Settings in the document SPRS439F, I don't think there are any allowed values for PLLCR[DIV] and PLLSTS[DIVSEL] that would result in a 150Mhz clock frequency.
The sprc675 Baseline Software has a flashing led example project. This example sets PLLCR[DIV] to 15 (0x0f) and does not touch PLLSTS[DIVSEL]. The boot rom leaves PLLSTS[DIVSEL] equal to 2. This appears to result in a clock frequency of 150MHz.
Is it ok to set PLLSTS[DIVSEL] to 15? Table 3-16 says this is a reserved value.
Quoting from Note 1 Table 3-16. PLL Settings in the document SPRS439F "By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1."
The flashing led example does not set PLLSTS[DIVSEL] to 0 before changing PLLCR[DIV].
The function InitPll in DSP2833x_SysCtrl.h from sprc530 seems to use the correct sequence to set up the PLL, however the file DSP2833x_Examples.h only lists the allowed values for PLLCR[DIV] of 0 to 10, it does not list the reserved value of 15.
I suspect this means that to get a 150MHz clock, I should change the crystal to a 30MHz crystal like in the ezDSP kit, or a 25MHz crystal as in the Rev 1.0 TMDSCNCD28335 controlCARD.
