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Data size selection for McBSP (F28M35)

Gabriel Brunheira
Intellectual 440 points

Hi everyone!

I want to send data from an external ADC to the c28 core of a F28M35 via SPI using the McBSP module. There are two reasons for that: increased clock speed and DMA capability.

Since I want to operate the ADC in max sample rate, its convenient to use it as the SPI Master, so the F28M35 must be Slave. The problem is: my ADC resolution is 18 bits, so the data size and the clock generated by it has only 18 bits.

If I set the McBSP data size to 20 bits, the McBSP module will wait for 2 more bits to pass the content from the RSR register to DRR (and generate an interrupt). But the ADC can't send dummy bits, when it's configured as SPI Master. So the next 2 bits would be the 2 MSB's from the next sample, which is an awful solution for that.

I thinked of using 2 frames per transmission: the first with 12 bits and the second with 24 bits. This way, I have 36 bits per transmission, i.e. 2 samples of 18 bits. But I requires some extra undesirable processing time.

Is there a better solution for my problem?

If I configure the McBSP as SPI Master, it could send 20 bits, and the ADC would return 20 bits, from which the 18 MSB's would be my current sample, and the 2 LSB's would be shifted out. But this way, I would waste too much time from the c28 to start the transmissions, which doesn't occur if the ADC is the SPI Master.

I could also use the SPI module to receive 2 packages of 9 bits, but I can't use the DMA funcionality.

Thanks in advance!

Gabriel

  • 0 in reply to Gabriel Brunheira
    TI__Genius 15260 points

    Gabriel,

    Unfortunately using the McBSP there is not a seamless solution for dealing with 18 bit transmissions in SPI mode.  There is going to some overhead no matter how you look at it.

    The only other possible solution I would have would be to tie a GPIO configured as XINT to your SPISTE signal from the ADC.  Generate an XINT on the rising edge, therefore you know the ADC has completed its entire 18 bit transfer, but the McBSP will not generate an interrupt since it is looking for 20 bits.  When you enter the XINT ISR, you should be able to read the shift registers (note NOT the RX registers since it will not have copied over yet).  I believe data is shifted in from the right side of the register (but not positive on that) so I don't think you would need to do any manual shifting.  The only remaining item would be to disable the McBSP ISR or find another way to prevent it from occurring since it would be irrelevant.

    Like I said, no clean method to do this.  Whatever works best for your application.

    Kris