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F2809 few questions adc, isr

Other Parts Discussed in Thread: TMS320F2809

Hello,

I`m using TMS320F2809 with 100MHz clock.

1. I would like to get some info about init of adc and then using it. There is a need to use two adc inputs but used independently, if i want to sample channel 0 should i do sth like?:

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
while(AdcRegs.ADCST.bit.SEQ1_BSY) {}; 
return AdcRegs.ADCRESULT0 >> 4;

and if i want to sample channel 1 do i need to change 0x0 to 0x1 only and the rest stays as it is?

and the initialisation of adc is here:

#define ADC_MODCLK 0x4 
#define ADC_CKPS   0x1  
#define ADC_SHCLK  0xf

AdcRegs.ADCTRL1.bit.ACQ_PS = ADC_SHCLK;     // s/h width in adc module periods
AdcRegs.ADCTRL3.bit.ADCCLKPS = ADC_CKPS;     // adc module clock = HSPCLK/2*ADC_CKPS
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;            // 1 - Cascaded mode
AdcRegs.ADCTRL1.bit.CONT_RUN = 0;             // Setup start/stop run (0)
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;        // adc0 channel
AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;         // Power up bandgap/ref cirq
DELAY_US(8000L);                                    // Minimum 7ms before powering up rest of ADC
AdcRegs.ADCTRL3.bit.ADCPWDN = 1;             // Power up rest of ADC
DELAY_US(100L);                                 // Delay before converting ADC channels (min 20us)

2. Do all ISR`s should be mapped to SARAM if i do boot to flash?

now i have:

#pragma CODE_SECTION(cpu_timer0_isr, "ramfuncs");
#pragma CODE_SECTION(scia_rx_isr, "ramfuncs");
#pragma CODE_SECTION(scib_rx_isr, "ramfuncs");

because for know i use three isrs. For now i`m writting the software without the board so i cant test my ideas.

Thanks for any help.

  • Leszek,

    This is correct, if you want to change the sampled channel to 1 from 0 that is all you need to do.  The MAXCONV bit field is by default 0, so you will only convert 1 channel for every SOC trigger received by the ADC.  If you want to convert channel 1 again you have 2 options:

    1)Reset the sequencer after each conversion

    2)Load the next CONVxx values with 1; such that channel 1 is converted in all sequencer slots.  

    Utilizing #2 you could maintain a 16 result history of the samples.

    Some other points to note:

    -F2809 ADC only requires 5ms of init time vs the 7 in your code.

    -All the power up bits can be set at the same time, and then wait 5ms

    -If you will be using the data in right justified format, there are right justified result registers @ 0xB00 that are pre-shifted and are 0WS access

    Finally for the ISR point, you should only have to populated those ISRs that will be enabled/used by the CPU in your code.  However, it might be wise to populate the error ISRs like TRAPs with something deterministic in case there are debug issues with the code.

    Best,

    Matthew   

  • Thanks for your reply.

    - I thought that i should power up bandgap & ref, a then after delay power up the rest of adc. I will change it.

    - Is that register holds only data from the last conversion? (edit: ooh, now i see 0xb00 - 0xb0f is the result registers, so the channel 0 - 0xb00, channel 1 - 0xb01?)

    - What do you mean by "isr that will be enabled/used by the cpu"?