Trouble with I2C interface on TMS320F28335

Dear all,

I'm on a firmware design for new system based on TMS320F28335 DSP. I have utilised the I2C bus for interfacing six port expander IC's and one RTC chip with main DSP. In my I2C driver, when I try to communicate, only address byte is seen on data lines. The signal starts with a start condition the slave address and stop conditions; but the data I've sent is completely disappearing.I'm really stuck with further development, can I know what could be the problem in I2C interface to act like this ? Is there some one who faced issue like this?

Thanks in advance

 

SAP

The signal starts with a start condition the slave address and stop conditions;

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You should receive a ACK, NACK or  Register Access Ready after sending the slave adress

So my first guess is that that the Register I2caRegs.I2CCNT is set to a wrong value, or maybe the I2caRegs.I2CMDR to initiatie the start.

You can find an example of I2C EEPPROM In the http://focus.ti.com/docs/toolsw/folders/print/sprc530.html hopes this will help.

Leo

 

 

hey Leo,

 

thanks 4 your help,its working now [:D]

Hi SAP

I'm having exactly the same problem with the I2C on the F28335. I'm using the header and example c files as recommended and I'm pretty sure the I2CNT and I2CMDR registers are set up properly, I have not changed the example.

When I load the code onto a EZdsp board that has just been powered, the EERPOM test passes, no problem. If I then restart the code, the eeprom test fails as the data sent is exactly what the address is.

Could you tell me how you solved your problem?

thanks

Even i m facing the same problem.

it runs for one time but then the BB bit remains high even when the stop bit is set.

according to stop bit (STP) condition in MDR register, the stop bit is sent after  transferring the number of bytes set in CNT register. When the code is executed for the 1st time. the bus is free and so there's no problem in the transfer. But after that BB remains high and so it doesnt work for the second time. If we reset the device(disconnect he device from CCS and then connect it again which makes the bus free) and then execute the code, it works .

I find that the problem seems to be related to the FIFO TX buffer size TXFFST register. On first transmission it is still empty, however when transmitting again (now buffer size 14) the buffer reaches it's maximum size of 16 and seemingly will not take on any more data after the address is bytes (2 + 14 = 16) are written to the I2CDXR register. I'm not clear from the documentation if after every transmit this buffer needs to be reset manually or not. It seems rather cumbersome to reset them manually so i'm probably not configuring some register correctly.

Any ideas?

Hi

I am facing problem on I2C interface (F28335) with EEPROM (AT24C1024B).

I was intialized slave address register by the salve address.The I2CCNT register intialized by 3.After that  i am trying to transmitt 3 bytes to the slave device  in Master Transmitter mode.After transmission of the 3 bytes the BB bit will goes to zero as per theory.But in my case it is not resetting to zero,it shows always one.

I am getting Register Access ready interrupt continuously.May i know what it is?

How can i know the slave is receiveing data from the master,is there any flags or interrupts,how can i know the communication establishment between master and reciver?

What i am doing wrong in my intializations,please send the chck list to fix this problem.

Thanks

Srinivas reddy

Hello Together,

Any solution here?

Hello Kristian,

This thread is pretty old and I'll be going off of the questions that Sirinivas last had. If you are looking for answers to different questions please let me know.

A good source of information on the I2C module for this specific device can be found in the TMS320x2833x, 2823x Inter-Integrated Circuit (I2C) Module Reference Guide. www.ti.com/.../sprug03b.pdf

One reason the BB bit may not be resetting is that the I2C peripheral is in the "reset" state. That is the IRS bit is set to 0 which will keep the BB bit in the state it was when placed in the "reset" state and it will stay in this state until it is taken out of reset (IRS bit set to 1). More information can be found on page 31 of the Reference Guide, with the steps provided.

Follow these steps before initiating the first data transfer with I2C :

1. After taking the I2C peripheral out of reset by setting the IRS bit to 1, wait a certain period to detect the
actual bus status before starting the first data transfer. Set this period larger than the total time taken
for the longest data transfer in the application. By waiting for a period of time after I2C comes out of
reset, users can ensure that at least one START or STOP condition will have occurred on the I2C bus,
and been captured by the BB bit. After this period, the BB bit will correctly reflect the state of the I2C
bus.
2. Check the BB bit and verify that BB=0 (bus not busy) before proceeding.
3. Begin data transfers.

Not resetting the I2C peripheral in between transfers ensures that the BB bit reflects the actual bus status.
If users must reset the I2C peripheral in between transfers, repeat steps 1 through 3 every time the I2C
peripheral is taken out of reset.

The Register-Access ready interrupt is used to state when the I2C modules are ready to be accessed as the previously programmed address/data/etc. has been used (I2CDXR or FIFO is ready). Depending on the mode the I2C module is in, the ARDY bit may be set after each transmitted bit. Look into section 3 and Table 10 of the I2C Reference Guide for more info on this.

To see if the slave device is receiving data from the master you can try using NACKINT or polling the NACK bit. The I2C master will receive an ACK from the slave if it is receiving (NACK is 0). Check the Ref guide for more info about NACKs.

Hope this helps,
Kevin