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TMS320F28234 ADC timing question

chuckwagon
Expert 3280 points

Hi Champs,

I have a question about how document SPRS439 describes the ADC timing. In document SPRS439 rev F, section 6.15.4 ("Simultaneous Sampling Mode (Dual_Channel) (SMODE=1)"), paragraph 1 (page 156), the fifth sentence states "The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update.". How many SYSCLKOUT cycles equals a "few"? Is there an exact timing relation ship between the final register update of the final sequencer conversion and the setting of the SEQ1INT latch (PIEIFR1.1)? I am trying to nail down the exact timing of the SEQ1INT after each conversion session. I am running ADC in continuous mode at the max clock rate (25 MHz) and am concerned about result register updates during the course of SEQ1INT processing.

Thanks in advance,

Chuck

  • 0
    TI__Guru* 84690 points

    Chuck,

    There is one ADC Clock cycle from result register update to SEQ1INT flag/signal coming active.  1 SYSCLK cycle after this to propagate to the PIE/external logic.  1 SYSCLK cycle after this the PIE will latch the signal starting the interrupt process.

    I believe the above is for 2833x device, so SYSCLK is 6x ADC Clock of 25MHz.

    Not sure of your setup, but one option with continuous mode is to use the sequencer override feature in cascaded mode, allowing you to ping/pong between RESULT0-7 and RESULT8-15(MAXCONV = 7) with interrupts gen'd on 7 and 15.  This ensures you won't have data overwrite as you could with RESULT0 with interrupt on RESULT15 if you are in full cascaded mode(MAXCONV = 15)

    Best,

    Matthew