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CCE bit of CAN not getting set

Anuj Maheshwari1
Prodigy 90 points

Other Parts Discussed in Thread: CONTROLSUITE

oid initECan(void)
{

/* Create a shadow register structure for the CAN control registers. This is
needed, since only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents or return
false data. This is especially true while writing to/reading from a bit
(or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanaShadow1;

//struct GPIO_MUX_REGS GpioMuxRegs;

asm(" EALLOW");

/* Configure eCAN pins for CAN operation using GPIO regs*/

//GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
//GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;

// eCAN control registers require 32-bit access.
// If you want to write to a single bit, the compiler may break this
// access into a 16-bit access. One solution, that is presented here,
// is to use a shadow register to force the 32-bit access.

// Read the entire register into a shadow register. This access
// will be 32-bits. Change the desired bit and copy the value back
// to the eCAN register with a 32-bit write.

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/

ECanaShadow1.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow1.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow1.CANTIOC.all;

ECanaShadow1.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow1.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow1.CANRIOC.all;

/* Configure eCAN for HECC mode using SCB bit- (reqd to access mailboxes 16 thru 31)
If HECC mode is not enabled, we are in SCC mode and only 0-15 Mailboxes can be accesed.*/
// HECC mode also enables time-stamping feature

ECanaShadow1.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow1.CANMC.bit.SCB = 1;
// ECanaShadow1.CANMC.bit.ABO = 1; // Auto Bus on
ECanaRegs.CANMC.all = ECanaShadow1.CANMC.all;

/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register may come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero

ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
// as a matter of precaution.

/* Clear all TAn bits */

ECanaRegs.CANTA.all = 0xFFFFFFFF;

/* Clear all RMPn bits */

ECanaRegs.CANRMP.all = 0xFFFFFFFF;

/* Clear all interrupt flag bits */

ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters */

ECanaShadow1.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow1.CANMC.bit.CCR = 1 ; // Set CCR = 1
ECanaRegs.CANMC.all = ECanaShadow1.CANMC.all;

ECanaShadow1.CANES.all = ECanaRegs.CANES.all;

// Wait until the CPU has been granted permission to change the configuration registers
do
{
ECanaShadow1.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow1.CANES.bit.CCE != 1 ); // Wait for CCE bit to be set..

ECanaShadow1.CANBTC.all = 0;
ECanaShadow1.CANBTC.bit.BRPREG = 9; // 1 Mbps @ 150 MHz SYSCLKOUT
ECanaShadow1.CANBTC.bit.TSEG2REG = 2;
ECanaShadow1.CANBTC.bit.TSEG1REG = 10;
ECanaShadow1.CANBTC.bit.SAM = 1;
ECanaRegs.CANBTC.all = ECanaShadow1.CANBTC.all;

ECanaShadow1.CANMC.all = ECanaRegs.CANMC.all;
ECanaShadow1.CANMC.bit.CCR = 0 ; // Set CCR = 0
ECanaRegs.CANMC.all = ECanaShadow1.CANMC.all;

ECanaShadow1.CANES.all = ECanaRegs.CANES.all;

ECanaShadow1.CANTRR.all = ECanaRegs.CANTRR.all;
ECanaShadow1.CANTRR.bit.TRR0 = 0;
ECanaShadow1.CANTRR.bit.TRR1 = 0;
ECanaRegs.CANTRR.all = ECanaShadow1.CANTRR.all;


// Wait until the CPU no longer has permission to change the configuration registers
do
{
ECanaShadow1.CANES.all = ECanaRegs.CANES.all;
} while(ECanaShadow1.CANES.bit.CCE != 0 ); // Wait for CCE bit to be cleared..

/* Disable all Mailboxes */
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.

ECanaRegs.CANME.all = 0; // Required before writing the MSGIDs
}

  • 0
    TI__Expert 8950 points

    Anuj,

    Can you please provide more information to help reproduce the problem? What part number are you using? Did you use the controlSUITE functions like InitSysCtrl() to initialize the system? Do you see this problem on multiple units, or just one?

    Thanks,

    -Adam

  • 0 in reply to Adam Haun
    Prodigy 90 points

    Thanks Adam for your response.

    But that problem is solved as i made some corrections in my code.I just wanted to ask that while can is sending data and receives acknowledgement can dsp perform any other work or it will just sit idle

    waiting for ur reply

  • 0 in reply to Anuj Maheshwari1
    TI__Expert 8950 points

    Yes, the C28 DSP can do other work while the CAN module is sending data. The CAN hardware is independent of the CPU.

  • 0 in reply to Adam Haun
    Intellectual 340 points

    I'm having the exact same problem with the CCE bit at the same point in the intiialization code on a 28069 eval board.  When I noticed that, I though I would just try and access some register to see if I can read and write them so I have this code below (I have verified the pCan pointer is pointing to 0x6000).  I just wanted to pick a register and see if I could write and read it successfully.  When I read the CANGIM register at the end of this snippet, I get all 0's.  In fact when I try this on any register I get all 0's so I don't know if the read or write (or both is broken).  So I guess, my first question would be to Anuj- what did you do to fixe the CCE problem?  I'm hoping this will fix my problem with the code below too!

    Thanks for any insight.

    struct ECAN_REGS ECanaShadow;

    EALLOW;

    ECanaShadow.CANGIM.all= pCan->CANGIM.all;

    ECanaShadow.CANGIM.bit.GIL= 1;
    ECanaShadow.CANGIM.bit.AAIM= 1;
    ECanaShadow.CANGIM.bit.WDIM= 1;
    pCan->CANGIM.all= ECanaShadow.CANGIM.all;

    ECanaShadow.CANGIM.all= 0;
    ECanaShadow.CANGIM.all= pCan->CANGIM.all;

    EDIS;

  • 0 in reply to Tom Tatakis
    Prodigy 100 points

    Im going to guess that you haven't enabled the eCan peripherial clock. You possibly haven't set up the GPIO Mux to allow the specific gpio pins to be used as CAN pins. Just my 2-cents.