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Power sequencing and GPIO pins

Hi:

From the datasheet for F2812:  "SPRS174o.pdf" notes on p. 99 it says: 

E. Since the state of GPIO pins is undefined until the 1.8-V (or 1.9 V) supply reaches at least 1 V, this supply should be ramped
   as quickly as possible (after the 3.3-V supply reaches at least 2.5 V).
F. Other than the power supply pins, no pin should be driven before the 3.3-V rail has been fully powered up.

If the GPIO are undefined until the 1.8V ramps up, then how can one be permitted to drive GPIO pins until this is so?  The datasheet appears to contradict itself.  It may be necessary, but not sufficient, to have the 3.3V ramped up before driving GPIO pins.  The reason being, that if the core is undefined, then a GPIO may inadvertently attempt to drive while the 3.3V IO supply enables it to do so.  Thus if an external driver is also attached to that pin, excessive current will flow.

Does anyone know the correct interpretation?  I am hoping that I can have external drivers attached to the pins which simply come up with the 3.3V supply.  But a strict interpretation suggests that the external drivers may need to be disabled until the core is active.  This could require a special GPIO and 3-stated drivers just for that, which is a pain.

Feedback will be appreciated!

Good day.

 

  • Hi Chris!

     

    There is a lot of confusion on proper power-up sequence. eZdsp schematics show delayed 1.8V rail ramp-up as do some of TI reference designs (PR412), while the other TI's reference designs show delayed 3.3V rail ramp-up (PR675 and PR676). Not to mention the device datasheets as you've mentioned. TI should really clean this mess they've made.

    I strongly recommend you to make a design where all three options of supply rails ramp-up are available (1.8V before 3.3V; 3.3V before 1.8V; 1.8 and 3.3V at the same time)

    From my experience (that is very design specific) bringing up 1.8V rail first is somewhat more robust.

    Regards, Mitja