Other Parts Discussed in Thread: TMS320F28335
hi all,
I am using TMS320F28335 as my processor and i am using DSP BIOS 5.33.03 , In my application i am using the internal ADC to get the voltage from 5 different inputs . And i tried this by not using the DSP BIOS . It works and interrupt comes correctly . But when i use the BIOS my ADC Interrupt Dosen’t occur, I hope my configurations are correct in BIOS and in my code. Please find my ADC driver below ,
Is their any thing which i need to take care when i am using the BIOS, In case of ADC . becoz i am using the CAN as well, Their the interrupt works correctly.
Hoping for the reply soon,
Regards,
SAP
CODE:
Void InitInternalAdc() {
EALLOW;
SysCtrlRegs.HISPCP.all = ADC_MODCLK; // HSPCLK = SYSCLKOUT/ADC_MODCLK
EDIS;
// The ADC_cal function, which copies the ADC calibration values from TI reserved
// OTP into the ADCREFSEL and ADCOFFTRIM registers, occurs automatically in the
// Boot ROM. If the boot ROM code is bypassed during the debug process, the
// following function MUST be called for the ADC to function according
// to specification. The clocks to the ADC MUST be enabled before calling this
// function.
// See the device data manual and/or the ADC Reference
// Manual for more information.
EALLOW;
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1;
ADC_cal();
EDIS;
// To powerup the ADC the ADCENCLK bit should be set first to enable
// clocks, followed by powering up the bandgap, reference circuitry, and ADC core.
// Before the first conversion is performed a 5ms delay must be observed
// after power up to give all analog circuits time to power up and settle
// Please note that for the delay function below to operate correctly the
// CPU_RATE define statement in the DSP2833x_Examples.h file must
// contain the correct CPU clock period in nanoseconds.
AdcRegs.ADCTRL3.all = 0x00E0; // Power up bandgap/reference/ADC circuits
DELAY_US(ADC_usDELAY); // Delay before converting ADC channels
// Enable ADCINT in PIE
// DINT;
// PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable PIE block
// PieCtrlRegs.PIEIER1.bit.INTx6 = 1; // Enable PIE Group 1 INT6
// IER |= M_INT1; // Enable CPU INT1
// EINT;
// ERTM;
// Configure ADC
AdcRegs.ADCMAXCONV.all = 0x0006; // Setup 6 conv's on SEQ AdcRegs.ADCCHSELSEQ1.bit.CONV00 = INTADC_CH0_IV5_EXT; AdcRegs.ADCCHSELSEQ1.bit.CONV01 = INTADC_CH1_V5EXT_AN; AdcRegs.ADCCHSELSEQ1.bit.CONV02 = INTADC_CH2_IVBATT_EXT3; AdcRegs.ADCCHSELSEQ1.bit.CONV03 = INTADC_CH3_IVBATT_EXT4; AdcRegs.ADCCHSELSEQ2.bit.CONV04 = INTADC_CH4_VBATT_AN; AdcRegs.ADCCHSELSEQ2.bit.CONV05 = INTADC_CH5_TEMP; AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
// Assumes ePWM1 clock is already enabled in InitSysCtrl();
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC from from CPMA on Upcount
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.half.CMPA = 0x0080; // Set compare A value
EPwm1Regs.TBPRD = 0xFFFF; // Set period for ePWM1
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // count up and start
} /* intAdcInit() */
interrupt Void IntADC_Isr() {
IADC_ChannelData[0][ConvCount] = (AdcRegs.ADCRESULT0 >> 4);
IADC_ChannelData[1][ConvCount] = (AdcRegs.ADCRESULT1 >> 4);
IADC_ChannelData[2][ConvCount] = (AdcRegs.ADCRESULT2 >> 4);
IADC_ChannelData[3][ConvCount] = (AdcRegs.ADCRESULT3 >> 4);
IADC_ChannelData[4][ConvCount] = (AdcRegs.ADCRESULT4 >> 4);
IADC_ChannelData[5][ConvCount] = (AdcRegs.ADCRESULT5 >> 4);
// If 10 conversions have been logged, start over
if (ConvCount == NUM_OF_SAMPLES) {
ConvCount = 0;
} else {
ConvCount++;
}
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; // Reset SEQ1
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1; // Clear INT SEQ1 bit
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE
return;
} /* IntADC_Isr() */
