help! TMS320F28335: question about the ePWM configuration for three phase full bridge IGBTs drive

Yqmeng,

There are two different modes to update the CMPA and CMPB registers. They can be updated in Shadow Mode or Immediate Mode. Both of these modes are detailed on page 35 of the TMS320x2833x, 2823x, EPWM Module Reference Guide:

http://focus.ti.com/lit/ug/sprug04/sprug04.pdf

The TBCTR also has the same load modes Shadow and Immediate. If you clear the register you should receive the underflow.

Regards,

Tim Love

Hi Tim

I have read the reference guide sprug04 and spru791c, but I have not found the notes of showing that the TBCTR also has the same load modes Shadow and Immediate, could you please explain it in detail?

Hi Tim

  It seems that I have found a bug about the ePWM module of the F28335 DSP, I am not sure if it is really a bug, could you please help me solve this problem? the problem is:

    the test program is the example code epwm_updown_aq in DSP2833x_v120 from the C/C++ Header Files and Peripheral Examples sprc530, then we add a timer interrupt rounting ISRTimer0 and revise the TBPRD to 7500. the interrupt period of ISRTimer0 is 100us, the period of the TBCTR counting from ZERO to TBPRD and from TBPRD to ZERO is also 100us. in Interrupt Service Routines ISRTimer0, we read the TBCTR to a  array cou_temp[1000] as follow, 

interrupt void ISRTimer0(void)

{

if(i<1000)

{

cou_temp[i]=EPwm1Regs.TBCTR;

i++;

}

else i=0;

PieCtrlRegs.PIEACK.all |= PIEACK_GROUP1;

return;

}

we think that the values in the array should  be equal exactly in theory if the precision of the counters of timer0 and TBCLK can be guaranteed. but we find the differences in the values of the array are big and the values of the array are increasing gradually.

could you please help me solve the problem or explain it? 

could you please tell me your email address so that I can send the test program to you? 

regards

yqmeng

yqmeng,

You are using two different times and they give seperate counts. It is possible that you have one configured with a prescaler and is not running at the same frequency. Can you check this?

Regards,

Tim Love

Hi Tim

the test program used by us is the example code epwm_updown_aq in DSP2833x_v120 from the C/C++ Header Files and Peripheral Examples sprc530,  the prescalers of the TIMER0 and TBCLK has been configured and is running at the same frequency 150MHz,

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;       // Clock ratio to SYSCLKOUT

in Up-Count Mode, the TBPRD is set as 14999, just as illustrated in ePWM document SPRU04.pdf. 

Hello yqmeng,

If you have the PWM configured in up-down count mode, TBCTR will be counting up from 0 to TBPRD for 100us and then counting down from TBPRD to 0 for the next 100us and so on. If your Timer0 configuration is correct and the interrupt is generated every 100us then one value would be read during the up count and the next value during the down count of TBPRD. Now these two values would be equal only if the ISR is generated just before the mid-point of the up-count and the down-count such that the TBCTR value is always read at te mid-point. If on the other hand the ISR is generated close to after 0 on the up count, the TBCTR value read will be close to zero. The next ISR is generated 100us later. At this time TBCTR would have just started decrementing from TBPRD. Thus the value read here will be close to TBRD. Thus the consecutive values in your array would be drastically different. However, every other value should be identical if all your timers are configured right.

Also, you have to ensure that the Timer0 interrupt is triggered every 100us i.e. there is no other interrupt that may keep this interrupt pending.

For a 3-phase full bridge drive it is common to use the PWM time-base to generate interrupts. The ePWM modules on the F28335 devices is very flexible in letting you generate different interrupts at various events.

Hope this helps.

Hrishi