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2407A ADC Clock

Russ5635
Prodigy 60 points

We have been using the 2407A for a few years and have always used the ADC at "full" speed (40MHz)(CPS = 0 and ACQ bits 0) with no apperant problems.

We are now updating our controller and sampling more channels and upon review of the TI ADC doumentation SPRS145J (datasheet) and SPRU357C (manual) there is some confusion about the ADC clock speed. The datasheet states that the clock cannot be greater than 30MHz but the manual uses examples using the 40MHz clock rate. The datasheet limitation tells me that the ADC cannot run at 40MHz and that the clock will have to be divided down.

Does this mean that CPS has to equal 1 for the 2407A so that the clock will now be 20MHz and is slower than the minimum cycle time of 33.3ns?

Also when I set CPS = 1 and leave the ACQ bits = 0 the ADC does not operate (all channels read a rail value). If I set CPS = 1 and ACQ bits to any value greater than 0 the ADC works properly.

Thanks in advance for any clarification on this,

Russ

  • Genius 5885 points

    Hi Russ

    The code examples were probably writen for the old 2407 DSPs (which ran at 30MHz) and not the new ones 2407A which run at 40MHz.

    You can run ADC at 40MHz, but it will not operate within specifed parameters. If you are satisfed with the performance (be sure to test it thoroughly it across whole operating range (temperature, 3.3V on one chanel 0V on the next chanel in sequence and vice versa) you can run it at full speed, but it is safer to run it within operational parameters.

    When CPS=1 and ACQ=0 there is a silicon bug. Read the errata.

     

    Regards, Mitja