Why do I get two unexpected spiTxFifoIsr() interrupts when using the TI demo SPI code?
I'm using the TI example code Example_280xSpi_FFDLB_int.c which demonstrates SPI using loopback mode, FIFO, and interrupts. I am using this as a template to configure an SPI slave that is not in loopback mode. I have modified the following TI initialization function as follows:
void spi_fifo_init()
{
// Initialize SPI FIFO registers
SpiaRegs.SPICCR.bit.SPISWRESET=0; // Reset SPI
/////////////////////////// Original TI Code/////////////////////////////////////////
// SpiaRegs.SPICCR.all=0x001F; //16-bit character, Loopback mode
// SpiaRegs.SPICTL.all=0x0017; //Interrupt enabled, Master/Slave XMIT enabled
//////////////////// Modified for Not-Loopback, Slave Mode////////////////////////
SpiaRegs.SPICCR.all=0x000F; //16-bit character, Not-Loopback mode
SpiaRegs.SPICTL.all=0x0013; //Interrupt enabled, Slave XMIT enabled
SpiaRegs.SPISTS.all=0x0000;
SpiaRegs.SPIBRR=0x0063; // Baud rate
SpiaRegs.SPIFFTX.all=0xC028; // Enable FIFO's, set TX FIFO level to 8
SpiaRegs.SPIFFRX.all=0x0028; // Set RX FIFO level to 8
SpiaRegs.SPIFFCT.all=0x00;
SpiaRegs.SPIPRI.all=0x0010;
SpiaRegs.SPICCR.bit.SPISWRESET=1; // Enable SPI
SpiaRegs.SPIFFTX.bit.TXFIFO=1;
SpiaRegs.SPIFFRX.bit.RXFIFORESET=1;
}
Whenever I run the code on an ezF2808 board I get two calls to the spiTxFifoIsr() ISR. I do not have a master SPI device connected to the SPI pins. I am monitoring the lines on a scope and none of them are being actived. I am confused as to why these intial two interrupts are occuring. Any thoughts?
-Scott
