F2812 external bus interface

Holger,

This will depend on a number of things.   What I can think of off the top of my head:

- Is the write buffer enabled or disabled?  If it is enabled, and not full, then the CPU will not wait for the write to complete before it goes off to do something else.  In this case the writes would get buffered up (until the buffer is full) and the chip select may stay low.  That is the writes will be back-to-back.

- All XINTF accesses begin on the rising edge of XCLKOUT.  XCLKOUT is equal to or 1/2 XTIMCLK.  XTIMCLK is either equal to or 1/2 SYSCLKOUT.  Depending on the ratio from SYSCLKOUT to XCLKOUT there may be cycles where the XINTF is waiting for a rising edge of XCLKOUT to begin the access.

- The CPU access itself could be stalled for some reason.  For example, wait states, memory access conflict or register conflict.

-Lori

Lori,

you mentioned a scenario where the chip select may stay low during consecutive (back-to-back) writes. Can you confirm that this is not possible for a write access followed by a read access (or vice versa), means that the chip select will definitely get inactive between such accesses?

In Figure 10 of the XINTF reference guide (spru067), there are waveforms shown for consecutive accesses without any delay or alignment cycles. Yes, there is a note saying that the diagram is conceptual and you should check the datasheet for the device-specific timings, but I couldn't get any more clarification there....

Thanks and Regards,

Ruppert

No, it doesn't matter what the type of accesses are. 

If two accesses are

1) to the same zone and

2) they occur back-to-back and

3) there is no need for any alignment cycles then

the chip select will remain low between the accesses.  Requiring the chip select to go high between accesses would only slow down the interface. 

Alignment cycles occur when an access timing is such that the start of the access does not align with the rising edge of XCLKOUT.  Read/write strobes will go low only after the lead portion of the access and then go high when the trail portion of the access begins.  Typically you will want a trail at least on write accesses.

Is there a reason customers want the chip select to go high between back-to-back accesses to the same zone?

-Lori

Lori,

many thanks for the clarification.

It's not necessarily that the customers want the CS to go high. It's more to do with timing considerations for slower external RAM devices.

Best Regards,

Ruppert