C2000 ePWM1/GPIO/ADC config F28335

Couple of clarifications:

1. Have you set CMPA and TBPRD values correctly for Epwm1A?  Whatever triggering you do with PWM, Finally what you see on the pin depends on tbprd and Cmpa value.

2. What do you mean by program freezes? Does it hit an ESTOP, does it get stuck somewhere, does the whole debugger window stops working, do you get any error indications. etc..

It actually gives the "Power Failure" message I previously described in the other thread. I started this new thread to try to do something that I'm wondering if it is actually possible to do. So when I enable the ADC on ePWM1, it runs fine. but when I enable the GPIO0 pullups, set direction, and assign the mux, that's when I get the error. The sample code I posted in the last thread is still current.

T

Hi Anthony,

Just to remove narrow down whether you are facing a hardware or a software problem, I suggest you try out the adc_soc example project. If that works fine then we can confidently start looking at the code for a bug.

Vivek

It does work. In fact, I've built several other files from that one already. None of which included ePWMs though...

Ok Vivek and anyone else out there who can answer this one.. 

So I'm attaching my code - I have the ADC on ePWM1, and I have ePWMs 2-5 enabled to output on their associated GPIO pins. When I comment out the line that starts ePWM1, there is no ADC SOC and all the other ePWMs output correctly - verified with an oscilloscope. When I enable ePWM1 for ADC SOC, the rest of the ePWMS stop working, and the ADC works (sort of - I think I'm gettig a few bogus numbers coming in...). I'm hoping it's not something simple and stupid, but I've checked over everyting a few times now. I'm lost!!

Tony

6567.test3.zip

Hi Anthony,

I don't see the ADCCLK and Sample and Hold clk settings done. The ADCCLK has a limitation. Maybe in your case it's operating beyond it's limitation. That could be the problem.

Vivek

Hey Vivek,

Hmmm. Funny... this was taken directly from the AdcSoc example file... I had assumed that since it was working there that it was all set... Do elaborate for me? ADCCLK setting was in the the beginning of the main program:

SysCtrlRegs.HISPCP.all = ADC_MODCLK;     // Define ADCCLK clock frequency, <=25 MHz - Assuming InitSysCtrl() has set SYSCLKOUT to 150 MHz

I didn't directly use any s/h settings since as I said, I just copied from Example_2833xAdcSoc.c

Elaborate a bit for me? I'm looking this up at the moment...

T

Vivek - I added the following to my setup code:

AdcRegs.ADCTRL3.bit.ADCCLKPS = 0; // Enable 25Mhz ADC Clock

AdcRegs.ADCTRL1.bit.CPS =0; //

AdcRegs.ADCTRL1.bit.ACQ_PS = 0; // 12.5 MHz / 12.5 MSPS sustained conversion rate  = 40ns SH width

I'm hoping that will fix it, I'll let you know.

T

Vivek - that didn't help. I still have no ePWM output.

Anthony Scarnici said:

When I comment out the line that starts ePWM1, there is no ADC SOC and all the other ePWMs output correctly - verified with an oscilloscope. When I enable ePWM1 for ADC SOC, the rest of the ePWMS stop working

Just another suggestion regarding this issue. To identify whether the problem is with ADC or ePWM1, just comment out the ePWM SOC line (I'm assuming you commented out the whole ePWM1 initialisation section and monitored only the other pwm pins correctly.) This will disable the start of conversion for the ADC. Then see if the ePWM 1 o/p is as expected.

Did that - ePWMs work when I don't enabe ADC SOC.

Hey TI employees,

Any Ideas why this doesn't work? I've changed configuratios several times in the hopes that it will, but for some reason, the ePWMs won't run when the ADC is running.

Hi Anthony,

I think i might have found out the bug. Going through the code line by line i saw that you have configured the sequencer in Simultaneous sampling cascaded mode. In this mode, every value in ADCMAXCONV corresponds to two actual conversions. This means that for 16 conversions you need to actually write a value of 7. Also CONV8 to CONV15 values make no sense in this mode.

Here's the correct initialization procedure straight from the datasheet.

AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1; // Setup simultaneous sampling mode
AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x1; // Setup cascaded sequencer mode
AdcRegs.ADCMAXCONV.all = 0x0007; // 8 double conv's (16 total)
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup conv from ADCINA0 &amp; ADCINB0
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup conv from ADCINA1 &amp; ADCINB1
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup conv from ADCINA2 &amp; ADCINB2
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup conv from ADCINA3 &amp; ADCINB3
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup conv from ADCINA4 &amp; ADCINB4
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup conv from ADCINA5 &amp; ADCINB5
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup conv from ADCINA6 &amp; ADCINB6
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup conv from ADCINA7 &amp; ADCINB7

Here's what you have done:

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA0 as 1st SEQ1 conversion => (x+Va)
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA1 as 2nd SEQ1 conversion => (x-Vb)
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3rd SEQ1 conversion => (x+Vb)
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA3 as 4th SEQ1 conversion => (x-Vc)
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA4 as 1st SEQ2 conversion => (x+Vc)
AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA5 as 2nd SEQ2 conversion => (X-Va)
AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA6 as 3rd SEQ2 conversion => (Vdc+)
AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA7 as 4th SEQ2 conversion => (Vdc-)
AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; // Setup ADCINB0 as 1st SEQ3 conversion => (x+Ia)
AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; // Setup ADCINB1 as 2nd SEQ3 conversion => (x-Ib)
AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; // Setup ADCINB2 as 3rd SEQ3 conversion => (x+Ib)
AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; // Setup ADCINB3 as 4th SEQ3 conversion => (x-Ic)
AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; // Setup ADCINB4 as 1st SEQ4 conversion => (x+Ic)
AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; // Setup ADCINB5 as 2nd SEQ4 conversion => (x-Ia)
AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; // Setup ADCINB6 as 3rd SEQ4 conversion => (ADC Vref+)
AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; // Setup ADCINB7 as 4th SEQ4 conversion => (extra - GND reference)

AdcRegs.ADCTRL3.bit.SMODE_SEL = 1; // Enable Simultaneous Sampling Mode.
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1; // Enable Operation as a Single 16-state Sequence - Cascade Mode.

Not sure what the result of wrong initialisations will be, but I think you are crashing the processor. 

Hoping this helps.

Vivek

Actually Vivek, I need to sample all 16 ADC inputs. These are the control signals from my system that I need to digitize. They are all referenced in the comments. All channels are sampling correctly, as far as I can tell, My problem lies in the fact that when the ADC is running, the pwms are not. I'm wondering if it is in the epwm setup, but I cannt tell. It all looks correct so far.

Wow, ok. I totally missed that, thank you. I'll let you know if it works! I would assume then that my initial sequence setup should be fine then?

Hey Vivek,

I think I figured it out.. somethig is fishy here...  I went through the GPIO registers in SPRUFB0D and found that my configuration was really bad - how in the world this works the way it was set up I'll never know. The problem is, when I wrote the original configuration, I was looking at the GPIO and ePWM assignments in the EZDSP booklet because I was looking to probe the outputs. The Book literally shows GPIO2 as EPWM2A, and GPIO4 as EPWM2B, and other wrong assignments... Where as SPRUFB0D has GPIO2 as EPWM2A and GPIO3 as EPWM2B and so on in succession... So I originally followed that pinout on the board when I set up the GPIO. The pinout shown on pp2-10 to 2-11 is rather confusing. I haven't run anything yet, but I'll update you when I test my new configuration.

Ok, here is my current ADC and ePWM configuration, and the ADC properly samples, and the ePWMs properly output:

AdcRegs.ADCTRL3.bit.ADCCLKPS = 0; // Core Clock divider -> 0 HSPCLK/(ADCTRL![7]+1)

AdcRegs.ADCTRL1.bit.CPS =0; // Core Clock Prescaler - ADCCLK = Fclk/1

AdcRegs.ADCTRL1.bit.ACQ_PS = 0; // 12.5 MHz / 12.5 MSPS sustained conversion rate  = 40ns SH width

AdcRegs.ADCTRL3.bit.SMODE_SEL = 0;     // Enable Sequential Sampling Mode.

AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;      // Enable Operation as a Single 16-state Sequence - Cascade Mode.

AdcRegs.ADCMAXCONV.all = 0x000F;       // Setup 16 conversions for cascade sequence

AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1; // Enable SOCA from ePWM to start SEQ1

AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;  // Enable SEQ1 interrupt (every EOS)

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; // Setup ADCINA0 as 1st SEQ1 conversion => (x+Va)

AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; // Setup ADCINA1 as 2nd SEQ1 conversion => (x-Vb)

AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x2; // Setup ADCINA2 as 3rd SEQ1 conversion => (x+Vb)

AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x3; // Setup ADCINA3 as 4th SEQ1 conversion => (x-Vc)

AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x4; // Setup ADCINA4 as 1st SEQ2 conversion => (x+Vc)

AdcRegs.ADCCHSELSEQ2.bit.CONV05 = 0x5; // Setup ADCINA5 as 2nd SEQ2 conversion => (X-Va)

AdcRegs.ADCCHSELSEQ2.bit.CONV06 = 0x6; // Setup ADCINA6 as 3rd SEQ2 conversion => (Vdc+)

AdcRegs.ADCCHSELSEQ2.bit.CONV07 = 0x7; // Setup ADCINA7 as 4th SEQ2 conversion => (Vdc-)

AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8; // Setup ADCINB0 as 1st SEQ3 conversion => (x+Ia)

AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9; // Setup ADCINB1 as 2nd SEQ3 conversion => (x-Ib)

AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0xA; // Setup ADCINB2 as 3rd SEQ3 conversion => (x+Ib)

AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0xB; // Setup ADCINB3 as 4th SEQ3 conversion => (x-Ic)

AdcRegs.ADCCHSELSEQ4.bit.CONV12 = 0xC; // Setup ADCINB4 as 1st SEQ4 conversion => (x+Ic)

AdcRegs.ADCCHSELSEQ4.bit.CONV13 = 0xD; // Setup ADCINB5 as 2nd SEQ4 conversion => (x-Ia)

AdcRegs.ADCCHSELSEQ4.bit.CONV14 = 0xE; // Setup ADCINB6 as 3rd SEQ4 conversion => (ADC Vref+)

AdcRegs.ADCCHSELSEQ4.bit.CONV15 = 0xF; // Setup ADCINB7 as 4th SEQ4 conversion => (extra - GND reference)

EPwm1Regs.ETSEL.bit.SOCAEN = 1;        // Enable SOC on A group

EPwm1Regs.ETSEL.bit.SOCASEL = 4;       // Select SOC from from CPMA on up-count

EPwm1Regs.ETPS.bit.SOCAPRD = 1;        // Generate pulse on 1st event

EPwm1Regs.CMPA.half.CMPA = 0x00BB;   // Set compare A value - duty cycle(%)=(CMPA*100/(TBPRD+1)) - set to 10% @ 40kHz

EPwm1Regs.TBPRD = 0x0EA6;              // Set period for ePWM1 - default: TBCLK=SYSCLKOUT/2 => TBPRD= 150MHZ/40kHz = 3750 = 0x0EA6 = 75MHz/20kHz

EALLOW;

// = = = = = = = = = = = = = = = = = = = = = = = =

EPwm2Regs.TBPRD = 3750; // Period = 3750 TBCLK counts (or 25 ms) since TBCLK = SYSCLKOUT

EPwm2Regs.CMPA.half.CMPA = 0x00BB; // Compare A = 350 TBCLK counts

EPwm2Regs.CMPB = 0x00BB; // Compare B = 200 TBCLK counts

//EPwm2Regs.TBPHS.half = 0x0000; // Set Phase register to zero

EPwm2Regs.TBCTR = 0; // clear TB counter

EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;

EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled

EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // disables sync mode

EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK

EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET;

EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm2Regs.AQCTLB.bit.ZRO = AQ_SET;

EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;

// = = = = = = = = = = = = = = = = = = = = = = = =

EPwm3Regs.TBPRD = 3750; // Period = 3750 TBCLK counts (or 25 ms) since TBCLK = SYSCLKOUT

EPwm3Regs.CMPA.half.CMPA = 0x01BB; // Compare A = 350 TBCLK counts

EPwm3Regs.CMPB = 0x01BB; // Compare B = 200 TBCLK counts

//EPwm3Regs.TBPHS.half = 0x0000; // Set Phase register to zero

EPwm3Regs.TBCTR = 0; // clear TB counter

EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;

EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled

EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // disables sync mode

EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK

EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET;

EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm3Regs.AQCTLB.bit.ZRO = AQ_SET;

EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;

// = = = = = = = = = = = = = = = = = = = = = = = =

EPwm4Regs.TBPRD = 3750; // Period = 3750 TBCLK counts (or 25 ms) since TBCLK = SYSCLKOUT

EPwm4Regs.CMPA.half.CMPA = 0x00BB; // Compare A = 350 TBCLK counts

EPwm4Regs.CMPB = 0x00BB; // Compare B = 200 TBCLK counts

//EPwm4Regs.TBPHS.half = 0x0000; // Set Phase register to zero

EPwm4Regs.TBCTR = 0; // clear TB counter

EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;

EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled

EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // disables sync mode

EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK

EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;

EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;

EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR;

// = = = = = = = = = = = = = = = = = = = = = = = =

EPwm5Regs.TBPRD = 3750; // Period = 3750 TBCLK counts (or 25 ms) since TBCLK = SYSCLKOUT

EPwm5Regs.CMPA.half.CMPA = 0x00BB; // Compare A = 350 TBCLK counts

EPwm5Regs.CMPB = 1875; // Compare B = 200 TBCLK counts

//wm5Regs.TBPHS.half = 0x0000; // Set Phase register to zero

EPwm5Regs.TBCTR = 0; // clear TB counter

EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_DOWN;

EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled

EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;

EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE; // disables sync mode

EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLK

EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;

EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR = Zero

EPwm5Regs.AQCTLA.bit.ZRO = AQ_SET;

EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;

EPwm5Regs.AQCTLB.bit.ZRO = AQ_SET;

EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR;

EDIS;

 I removed any setup for ePWM1 because it was causing trouble at the time. Can I use the same format above to have it drive GPIO0 and also the ADC SOC?  Also, if you'll notice, the following line is commented out on all the ePWM setups because I kept getting "integer value not allowed" when it compiled:

EPwm5Regs.TBPHS.half = 0x0000; // Set Phase register to zero

 So all I need to know is if I can setup GPIO0 and the ADC SOC to be driven by ePWM1. Thanks!!

Tony

Fasil,

I'm sorry, I cannot share that program with you. It is proprietary to my company, and I'm not allowed to share it. Sorry.