F2810 SPI problem

Todd,

 I'm unsure what you mean by the transmission complete flag. Im not aware of this kind of flag on the 281x SPI.

If the customer is not using the FIFO:  In the 281x SPI, the SPIST register has a "TXBUF FULL FLAG", which is set when a word gets written into the SPI transmit buffer (SPITXBUF) - this word is automatically loaded into the SPIDAT register and transmitted out the 281x, at which time the TXBUF FULL FLAG is cleared.  This may be why the customer is sometimes reading 0 and sometimes reading 1 (due to the automatic clearing of the bit, meaning a new word can be written).

Once that flag is cleared, the user can write another word to the SPITXBUF register. If there is still data in the SPITXBUF register, the TXBUF FULL FLAG will read 1, and the user should NOTwrite another word to SPITXBUF.

Once TXBUF FULL FLAG = 0, the user can write the next word. 

If your customer is using the FIFO- then he/she can monitor the SPIFFTX register, which is constantly updating as the FIFO moves the data.

Sorry to trouble you!

I have the same questions,and when i write some bytes to FIFO,SpiaRegs.SPIFFTX.TXFFST is always zero.

After executing SPIFFTX.bit.TXFFINTCLR=1; the TXFFINT is still 1,it donnot be cleared.So why?

I need your help,thanks a lot for your help!(I use f28027 with TI example and it works in FIFO mode. Example filename:spi_loopback_interrupts)

More questions:

1.In FIFO mode,how it generates the first interrupt then go to spiTxFifoIsr when it is doing for(;;)loop???(in TI Example  Example filename:spi_loopback_interrupts)

2.In FIFO mode,the send interrupt service routine is to send data like SpiaRegs.SPITXBUF=sdata[i],but the receive interrupt service routine is to store the received data to our specified array,it means SPIRXBUFF has received the data ,then store it,so what is difference?

3.When it have received data,it go to spiRxFifoIsr to store data with array rdata[ ] .This is easy to understand.But when it send data,how it do?

for(i=0;i<2;i++)
{
SpiaRegs.SPITXBUF=sdata[i]; // Send data
}

can we move the above-mentioned code out of spiTxFifoIsr?If we understand it like receive ,the send data action should have done bofore it go to spiTxFifoIsr ,so we can move it out.

But if it cannot, it must be a difference from spiTxFifoIsr and spiRxFifoIsr.

I need your help. i am waiting for your reply.

thanks a lot

Yang:

The answers to your questions are below:

yang zou said:

I have the same questions,and when i write some bytes to FIFO,SpiaRegs.SPIFFTX.TXFFST is always zero.

After executing SPIFFTX.bit.TXFFINTCLR=1; the TXFFINT is still 1,it donnot be cleared.So why?

The reason for this is that the SPIPRI[SOFT] bit = 1 - which means that the SPI continues transmitting even if you are single-stepping through your code or setting a breakpoint in your code. 

Therefore as soon as you write data to SpiaRegs.TXBUF, the SPI transmits and empties the FIFO (TXFFST = 0 then). Likewise, as soon as you set TXFFINTCLR = 1, the transmit buffer is empty again (because the SPI transmits), and so TXFFINT is reset to 1.  

If you set your debugger for real-time mode, and set your watch window to continuous refresh, you will see the level of TXFFST change and TXFFINT constantly switches from 0 to 1 and back again.

Additionally, if you want to be able to see TXFFST and TXFFINT change as you single step through your code, set the SPIPRI[SOFT] bit to 0 instead of 1.

yang zou said:

More questions:

1.In FIFO mode,how it generates the first interrupt then go to spiTxFifoIsr when it is doing for(;;)loop???(in TI Example  Example filename:spi_loopback_interrupts)

Whenever TXFFST < TXFFIL then the Tx FIFO will generate an interrupt. In other words, if there is still room in the FIFO to add more data, then the Tx FIFO will interrupt to allow you to write more data to the buffer.

yang zou said:

2.In FIFO mode,the send interrupt service routine is to send data like SpiaRegs.SPITXBUF=sdata[i],but the receive interrupt service routine is to store the received data to our specified array,it means SPIRXBUFF has received the data ,then store it,so what is difference?

• The TxFIFO ISR is triggered when the FIFO has empty slots for the application to write more data into the FIFO via SPITXBUF.
• The RxFIFO ISR is triggered when RXFFST >= RXFFIL (or when the FIFO has received the configured amount of data)  so user can read RXFFIL # of data words from the FIFO via SPIRXBUF.

yang zou said:

3.When it have received data,it go to spiRxFifoIsr to store data with array rdata[ ] .This is easy to understand.But when it send data,how it do?

for(i=0;i<2;i++)
{
SpiaRegs.SPITXBUF=sdata[i]; // Send data
}

can we move the above-mentioned code out of spiTxFifoIsr?If we understand it like receive ,the send data action should have done bofore it go to spiTxFifoIsr ,so we can move it out.

But if it cannot, it must be a difference from spiTxFifoIsr and spiRxFifoIsr.

For an explanation of how the SPI Tx FIFO and interrupt works, see my answer to #2. You can also disable Tx FIFO ISR interrupts if you like and manually write to SPITXBUF, but in your code be sure to check that TXFFST  == 0 before writing TXFFIL # of words to SPITXBUF. Otherwise you may overflow the FIFO...

I hope this helps!

I am really  deeply grateful for your help! I asked many people,but they donnot reply to me.(I am so sad,maybe they are very busy with their jobs)

After reading your explanation,I understand clearly.And another question:

The TxFIFO ISR is triggered when the FIFO has empty slots for the application to write more data into the FIFO via SPITXBUF.

But when the data will be sent out,is it after executing SpiaRegs.SPITXBUF=sdata[i]???

There is a sentence in SPI datasheet about SPITXBUF "In master mode, if no transmission is currently active, writing to this register initiates a transmission in the

same manner that writing to SPIDAT does

 will never be

Your reply helps me a lot!

I am so sorry to the format,please read it as following:

I am really deeply grateful for your help! I asked many people,but they donnot reply to me.(I am so sad,maybe they are very busy with their jobs)

After reading your explanation,I understand clearly.And another question:

The TxFIFO ISR is triggered when the FIFO has empty slots for the application to write more data into the FIFO via SPITXBUF.

But when the data will be sent out,is it after executing SpiaRegs.SPITXBUF=sdata[i]???

There is a sentence in SPI datasheet about SPITXBUF "In master mode, if no transmission is currently active, writing to this register initiates a transmission in the same manner that writing to SPIDAT does."

 Is it means when the first data is written to FIFO,it will be sent out immediately(on each clock pulse)?If I understand like this,FIFO will never be full??

Your reply helps me a lot!

I still so sad with my project,and many questions trouble me.

1. if  SpiaRegs.SPIPRI.bit.free=1,my project cannot work well!(not using single step)

2.if i set SpiaRegs.SPIFFTX.bit.TXFFIENA=0,when i am single-steping,TXFFINT is 1.why?On page 20,sprug71b,it need both SPIFFENA=1 and TXFFIENA=1.

and i found in spi_fifo_init() funciton,after  executing SpiaRegs.SPIFFTX.bit.TXFIFO=1 (//Re-enable Transmit FIFO operation),it set 1,no matter SpiaRegs.SPIFFTX.bit.TXFFIENA=0 or 1, is it strange???

3.the last question,when the code runs normally(not in single step),when the data is sent out???

After executing SpiaRegs.SPITXBUF=sdata[i]??? If it is,the FIFO is never be full,and when it goes to the first ISR,will it goes to