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ADC simultaneous sampling configuration

Other Parts Discussed in Thread: TMS320F2808

Hello.

I'm trying to play with ADC on TMS320F2808 and found the following example code of ADC setup:

       AdcRegs.ADCTRL1.bit.RESET = 1;
       asm(" RPT #22 || NOP");
       AdcRegs.ADCREFSEL.bit.REF_SEL = 0;
       AdcRegs.ADCTRL3.bit.ADCBGRFDN = 0x3;    /* ADCBGRFDN, reference power, 00=off, 11=on */
       AdcRegs.ADCTRL3.bit.ADCPWDN = 0x1;      /* bit5(1): ADCPWDN, main ADC power, 0=off, 1=on */
       AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x2; // 0x4    /* ADCLK=HSPCLK/[(2*ADCCLKPS)*(ADCTRL1[7] + 1)] */
       AdcRegs.ADCTRL3.bit.SMODE_SEL = 0x1;    /* 0=sequential sampling, 1=simultaneous sampling */
       DELAY_US(ADC_usDELAY);         // Delay before converting ADC channels

       AdcRegs.ADCMAXCONV.all = 0x0033;        /* 8 double conv's (16 total) */

Next 4 lines should setup both Ax & Bx acquisition at once as documenation has stated:

       AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;  //  INA0 & B0
       AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1;  //  INA1 & B1
       AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0xa;  //  INB2 & B2
       AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0xb;  //  INB3 & B3

But I'm confused in the following 4 lines:

       AdcRegs.ADCCHSELSEQ3.bit.CONV08 = 0x8;  //  INB0
       AdcRegs.ADCCHSELSEQ3.bit.CONV09 = 0x9;  //  INB1
       AdcRegs.ADCCHSELSEQ3.bit.CONV10 = 0x2;  //  INA2
       AdcRegs.ADCCHSELSEQ3.bit.CONV11 = 0x3;  //  INA3

What means configuration above? Which inputs I'll get in ADCRESULTxx?

       AdcRegs.ADCTRL1.bit.RESET = 0x0;        /* bit14(0): RESET, 0=no action, 1=reset ADC */
       AdcRegs.ADCTRL1.bit.SUSMOD = 0x00;      /* bit13-12(00): emulation suspend is ignored */
       AdcRegs.ADCTRL1.bit.ACQ_PS = 0x01;      /* bit11-8(0111): ACQ_PS (Acquisition) */
       AdcRegs.ADCTRL1.bit.CPS = 0x0;          /* bit7(0): 0: ADCCLK=FCLK/1, 1: ADCCLK=FCLK/2 */
       AdcRegs.ADCTRL1.bit.CONT_RUN = 0x0;     /* 0=start/stop mode, 1=continuous run */
       AdcRegs.ADCTRL1.bit.SEQ_OVRD = 0x0;     /* 0=disabled, 1=enabled */
       AdcRegs.ADCTRL1.bit.SEQ_CASC = 0x0;     /* 0=dual sequencer, 1=cascaded sequencer */

       AdcRegs.ADCTRL2.all = 0x0000;
       AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;
       AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ2 = 1;

Thank you in advance.

  • Anton,

    The example code you pasted is a bit odd looking.  I don't know what it was designed to do, but I can decipher it.  First, know that there are two different choices you need to make for the ADC: (1) cascaded vs. dual sequencer, and (2) sequential vs. simultaneous sampling.  In the code you show, it is doing dual sequencer (ADCTRL1.SEQ_CASC = 0x0) and simultaneous sampling (ADCTRL3.SMODEL_SEL = 0x1).  You also have ADCMAXCONV = 0x0033, which means that each sequencer is configured to do 4 (double) conversions.  Therefore, sequencer #1 will use CONV00 to CONV03, and sequencer #2 will use CONV08 to CONV11 for the first triggered conversion of each sequencer.  After the first triggered conversion, I think the expectation in your code is that the sequencer pointer is reset in the ISR (otherwise, you would move on to use the next four CONVxx registers in sequence).

    For the CONVxx setup, only the 3 LSBs are used in simultaneous sampling mode (bit 4 is ignored, per page 15 of SPRU716C F280x ADC User's Guide).  So, your code says to convert:

    Sequencer #1:
    CONV00 = 0x0 = 0000b ==> 000b ==> A0 & B0  in RESULT0,1
    CONV01 = 0x1 = 0001b ==> 001b ==> A1 & B1  in RESULT2,3
    CONV02 = 0xa = 1010b ==> 010b ==> A2 & B2  in RESULT4,5
    CONV03 = 0xb = 1011b ==> 011b ==> A3 & B3  in RESULT6,7

    Sequencer #2:
    CONV00 = 0x8 = 1000b ==> 000b ==> A0 & B0  in RESULT8,9
    CONV01 = 0x9 = 1001b ==> 001b ==> A1 & B1  in RESULT10,11
    CONV02 = 0x2 = 0010b ==> 010b ==> A2 & B2  in RESULT12,13
    CONV03 = 0x3 = 0011b ==> 011b ==> A3 & B3  in RESULT14,15

    So as I said, the code you show looks weird.  Not sure why someone would configure dual sequencer and then have each sequencer convert the same input channels.  Again, I don't know what this code is, nor where it came from.

    As a side note, I always specify the "A" channel for CONVxx in my code when I configure for simultaneous sampling.  The code is less confusing that way.

    Regards,

    David

     

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